当前位置： 首页 > news >正文

stm32 hal库spi dma_tx_rx的几个关键函数执行过程jlink trace分析

news 2025/8/28 10:51:04

1. spi_rx_dma

  • DMA2_Stream0_IRQHandler中调用HAL_DMA_IRQHandler, 在HAL_DMA_IRQHandler中调用了SPI_DMAReceiveCplt
  • 在SPI_DMAReceiveCplt中，判断RxDMA是以非DMA_CIRCULAR初始化的, 于是开启了__HAL_SPI_ENABLE_IT(hspi, SPI_IT_EOT)中断，这个中断使能触发了SPI中断。
Breakpoint 3, DMA2_Stream0_IRQHandler () at libraries\HAL_Drivers\drivers\drv_spi.c:712
712	    rt_base_t level = rt_hw_interrupt_disable();
rt_hw_interrupt_disable () at rt-thread\libcpu\arm\cortex-m7/context_gcc.S:39
39	    MRS     r0, PRIMASK
40	    CPSID   I
41	    BX      LR
DMA2_Stream0_IRQHandler () at libraries\HAL_Drivers\drivers\drv_spi.c:714
714	    HAL_DMA_IRQHandler(&spi_bus_obj[SPI1_INDEX].dma.handle_rx);
HAL_DMA_IRQHandler (hdma=0x240557c4 <spi_bus_obj+144>) at libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dma.c:1212
1212	  __IO uint32_t count = 0U;
1213	  uint32_t timeout = SystemCoreClock / 9600U;
1216	  DMA_Base_Registers  *regs_dma  = (DMA_Base_Registers *)hdma->StreamBaseAddress;
1217	  BDMA_Base_Registers *regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress;
1219	  tmpisr_dma  = regs_dma->ISR;
1220	  tmpisr_bdma = regs_bdma->ISR;
1222	  if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U)  /* DMA1 or DMA2 instance */
1225	    if ((tmpisr_dma & (DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)
1240	    if ((tmpisr_dma & (DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)
1252	    if ((tmpisr_dma & (DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)
1264	    if ((tmpisr_dma & (DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)
1266	      if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != 0U)
1269	        regs_dma->IFCR = DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU);
1272	        if(((((DMA_Stream_TypeDef   *)hdma->Instance)->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0U)
1296	          if((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_CIRC) == 0U)
1299	            ((DMA_Stream_TypeDef   *)hdma->Instance)->CR  &= ~(DMA_IT_HT);
1302	          if(hdma->XferHalfCpltCallback != NULL)
1305	            hdma->XferHalfCpltCallback(hdma);
SPI_DMAHalfReceiveCplt (hdma=0x240557c4 <spi_bus_obj+144>) at libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_spi.c:3444
3444	  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)
3450	  HAL_SPI_RxHalfCpltCallback(hspi);
HAL_SPI_RxHalfCpltCallback (hspi=0x24055734 <spi_bus_obj>) at libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_spi.c:3211
3211	}
SPI_DMAHalfReceiveCplt (hdma=0x240557c4 <spi_bus_obj+144>) at libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_spi.c:3452
3452	}
HAL_DMA_IRQHandler (hdma=0x240557c4 <spi_bus_obj+144>) at libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dma.c:1311
1311	    if ((tmpisr_dma & (DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)
1313	      if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != 0U)
1316	        regs_dma->IFCR = DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU);
1318	        if(HAL_DMA_STATE_ABORT == hdma->State)
1345	        if(((((DMA_Stream_TypeDef   *)hdma->Instance)->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0U)
1369	          if((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_CIRC) == 0U)
1372	            ((DMA_Stream_TypeDef   *)hdma->Instance)->CR  &= ~(DMA_IT_TC);
1375	            hdma->State = HAL_DMA_STATE_READY;
1378	            __HAL_UNLOCK(hdma);
1381	          if(hdma->XferCpltCallback != NULL)
1384	            hdma->XferCpltCallback(hdma);
SPI_DMAReceiveCplt (hdma=0x240557c4 <spi_bus_obj+144>) at libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_spi.c:3370
3370	  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3372	  if (hspi->State != HAL_SPI_STATE_ABORT)
3374	    if (hspi->hdmarx->Init.Mode == DMA_CIRCULAR)
3385	      __HAL_SPI_ENABLE_IT(hspi, SPI_IT_EOT); /*重点*/
3388	}
HAL_DMA_IRQHandler (hdma=0x240557c4 <spi_bus_obj+144>) at libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dma.c:1391
1391	    if(hdma->ErrorCode != HAL_DMA_ERROR_NONE)
1566	}
DMA2_Stream0_IRQHandler () at libraries\HAL_Drivers\drivers\drv_spi.c:717
717	    rt_hw_interrupt_enable(level);
rt_hw_interrupt_enable () at rt-thread\libcpu\arm\cortex-m7/context_gcc.S:49
49	    MSR     PRIMASK, r0
50	    BX      LR
DMA2_Stream0_IRQHandler () at libraries\HAL_Drivers\drivers\drv_spi.c:718
718	}
rt_hw_interrupt_enable () at rt-thread\libcpu\arm\cortex-m7/context_gcc.S:50
50	    BX      LR
Continuing.
  • SPI_DMAReceiveCplt函数重点，根据不同的DMA模式，做不同的处理
  • 对于DMA Circula模式，直接执行HAL_SPI_RxCpltCallback回调
  • 对于DMA_Normal模式，开启SPI_IT_EOT中断， 当SPI_IT_EOT中断触发时，执行HAL_SPI_RxCpltCallback回调
static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
{SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;if (hspi->State != HAL_SPI_STATE_ABORT){if (hspi->hdmarx->Init.Mode == DMA_CIRCULAR){
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)hspi->RxCpltCallback(hspi);
#elseHAL_SPI_RxCpltCallback(hspi);
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */}else{/* Enable EOT interrupt */__HAL_SPI_ENABLE_IT(hspi, SPI_IT_EOT);}}
}
  • SPI1_IRQHandler
  • 这个函数主要是执行了HAL_SPI_RxCpltCallback回调函数, 在这个回调函数中执行rt_completion_done
  • rt_completion_done执行了非常多的动作。这个可以不用管。
Breakpoint 1, SPI1_IRQHandler () at libraries\HAL_Drivers\drivers\drv_spi.c:695
695	    rt_base_t level = rt_hw_interrupt_disable();
rt_hw_interrupt_disable () at rt-thread\libcpu\arm\cortex-m7/context_gcc.S:39
39	    MRS     r0, PRIMASK
40	    CPSID   I
41	    BX      LR
SPI1_IRQHandler () at libraries\HAL_Drivers\drivers\drv_spi.c:696
696	    HAL_SPI_IRQHandler(&spi_bus_obj[SPI1_INDEX].handle);
HAL_SPI_IRQHandler (hspi=0x24055734 <spi_bus_obj>) at libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_spi.c:2888
2888	  uint32_t itsource = hspi->Instance->IER;
2889	  uint32_t itflag   = hspi->Instance->SR;
2890	  uint32_t trigger  = itsource & itflag;
2891	  uint32_t cfg1     = hspi->Instance->CFG1;
2892	  uint32_t handled  = 0UL;
2894	  HAL_SPI_StateTypeDef State = hspi->State;
2896	  __IO uint16_t *prxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->RXDR));
2900	  if (HAL_IS_BIT_SET(itflag, SPI_FLAG_SUSP) && HAL_IS_BIT_SET(itsource, SPI_FLAG_EOT))
2915	  if (HAL_IS_BIT_CLR(trigger, SPI_FLAG_OVR) && HAL_IS_BIT_CLR(trigger, SPI_FLAG_UDR) && \
2916	      HAL_IS_BIT_SET(trigger, SPI_FLAG_DXP))
2915	  if (HAL_IS_BIT_CLR(trigger, SPI_FLAG_OVR) && HAL_IS_BIT_CLR(trigger, SPI_FLAG_UDR) && \
2924	  if (HAL_IS_BIT_CLR(trigger, SPI_FLAG_OVR) && HAL_IS_BIT_SET(trigger, SPI_FLAG_RXP) && \
2932	  if (HAL_IS_BIT_CLR(trigger, SPI_FLAG_UDR) && HAL_IS_BIT_SET(trigger, SPI_FLAG_TXP) && \
2947	  if (handled != 0UL)
2953	  if (HAL_IS_BIT_SET(trigger, SPI_FLAG_EOT))
2956	    __HAL_SPI_CLEAR_EOTFLAG(hspi);
2957	    __HAL_SPI_CLEAR_TXTFFLAG(hspi);
2958	    __HAL_SPI_CLEAR_SUSPFLAG(hspi);
2961	    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_EOT);
2964	    if (HAL_IS_BIT_CLR(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN))
2997	    SPI_CloseTransfer(hspi);
SPI_CloseTransfer (hspi=0x24055734 <spi_bus_obj>) at libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_spi.c:3893
3893	  uint32_t itflag = hspi->Instance->SR;
3895	  __HAL_SPI_CLEAR_EOTFLAG(hspi);
3896	  __HAL_SPI_CLEAR_TXTFFLAG(hspi);
3899	  __HAL_SPI_DISABLE(hspi);
3902	  __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_TXP | SPI_IT_RXP | SPI_IT_DXP | SPI_IT_UDR | SPI_IT_OVR | \
3906	  CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN);
3909	  if (hspi->State != HAL_SPI_STATE_BUSY_RX)
3919	  if (hspi->State != HAL_SPI_STATE_BUSY_TX)
3921	    if ((itflag & SPI_FLAG_OVR) != 0UL)
3941	  if ((itflag & SPI_FLAG_MODF) != 0UL)
3948	  if ((itflag & SPI_FLAG_FRE) != 0UL)
3954	  hspi->TxXferCount = (uint16_t)0UL;
3955	  hspi->RxXferCount = (uint16_t)0UL;
3956	}
HAL_SPI_IRQHandler (hspi=0x24055734 <spi_bus_obj>) at libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_spi.c:2999
2999	    hspi->State = HAL_SPI_STATE_READY;
3000	    if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
3026	    if (State == HAL_SPI_STATE_BUSY_TX_RX)
3030	    else if (State == HAL_SPI_STATE_BUSY_RX)
3032	      HAL_SPI_RxCpltCallback(hspi);
HAL_SPI_RxCpltCallback (hspi=0x24055734 <spi_bus_obj>) at libraries\HAL_Drivers\drivers\drv_spi.c:1054
1054	    struct stm32_spi *spi_drv =  rt_container_of(hspi, struct stm32_spi, handle);
1055	    rt_completion_done(&spi_drv->cpt);
rt_completion_done (completion=0x2405593c <spi_bus_obj+520>) at rt-thread\components\drivers\ipc\completion_comm.c:21
21	    rt_completion_wakeup_by_errno(completion, -1);
rt_completion_wakeup_by_errno (completion=0x2405593c <spi_bus_obj+520>, thread_errno=-1) at rt-thread\components\drivers\ipc\completion_up.c:189
189	    RT_ASSERT(completion != RT_NULL);
191	    level = rt_spin_lock_irqsave(&_completion_lock);
rt_spin_lock_irqsave (lock=0x2405c0a8 <_completion_lock>) at rt-thread\src\cpu_up.c:67
67	    level = rt_hw_interrupt_disable();
rt_hw_interrupt_disable () at rt-thread\libcpu\arm\cortex-m7/context_gcc.S:39
39	    MRS     r0, PRIMASK
40	    CPSID   I
41	    BX      LR
rt_spin_lock_irqsave (lock=0x2405c0a8 <_completion_lock>) at rt-thread\src\cpu_up.c:68
68	    rt_enter_critical();
rt_enter_critical () at rt-thread\src\scheduler_up.c:507
507	    level = rt_hw_interrupt_disable();
rt_hw_interrupt_disable () at rt-thread\libcpu\arm\cortex-m7/context_gcc.S:39
39	    MRS     r0, PRIMASK
40	    CPSID   I
41	    BX      LR
rt_enter_critical () at rt-thread\src\scheduler_up.c:513
513	    rt_scheduler_lock_nest ++;
514	    critical_level = rt_scheduler_lock_nest;
517	    rt_hw_interrupt_enable(level);
rt_hw_interrupt_enable () at rt-thread\libcpu\arm\cortex-m7/context_gcc.S:49
49	    MSR     PRIMASK, r0
50	    BX      LR
rt_enter_critical () at rt-thread\src\scheduler_up.c:519
519	    return critical_level;
520	}
rt_spin_lock_irqsave (lock=0x2405c0a8 <_completion_lock>) at rt-thread\src\cpu_up.c:70
70	    return level;
71	}
rt_completion_wakeup_by_errno (completion=0x2405593c <spi_bus_obj+520>, thread_errno=-1) at rt-thread\components\drivers\ipc\completion_up.c:192
192	    if (RT_COMPLETION_FLAG(completion) == RT_COMPLETED)
198	    suspend_thread = RT_COMPLETION_THREAD(completion);
199	    if (suspend_thread)
203	        if (thread_errno >= 0)
208	        error = rt_thread_resume(suspend_thread);
rt_thread_resume (thread=0x2405ebe0) at rt-thread\src\thread.c:1017
1017	    RT_ASSERT(thread != RT_NULL);
1018	    RT_ASSERT(rt_object_get_type((rt_object_t)thread) == RT_Object_Class_Thread);
rt_object_get_type (object=0x2405ebe0) at rt-thread\src\object.c:587
587	    RT_ASSERT(object != RT_NULL);
589	    return object->type & ~RT_Object_Class_Static;
590	}
rt_thread_resume (thread=0x2405ebe0) at rt-thread\src\thread.c:1022
1022	    rt_sched_lock(&slvl);
rt_sched_lock (plvl=0x24001100) at rt-thread\src\scheduler_up.c:114
114	    if (!plvl)
117	    level = rt_hw_interrupt_disable();
rt_hw_interrupt_disable () at rt-thread\libcpu\arm\cortex-m7/context_gcc.S:39
39	    MRS     r0, PRIMASK
40	    CPSID   I
41	    BX      LR
rt_sched_lock (plvl=0x24001100) at rt-thread\src\scheduler_up.c:118
118	    *plvl = level;
120	    return RT_EOK;
121	}
rt_thread_resume (thread=0x2405ebe0) at rt-thread\src\thread.c:1024
1024	    error = rt_sched_thread_ready(thread);
rt_sched_thread_ready (thread=0x2405ebe0) at rt-thread\src\scheduler_comm.c:109
109	    if (!rt_sched_thread_is_suspended(thread))
rt_sched_thread_is_suspended (thread=0x2405ebe0) at rt-thread\src\scheduler_comm.c:83
83	    return (RT_SCHED_CTX(thread).stat & RT_THREAD_SUSPEND_MASK) == RT_THREAD_SUSPEND_MASK;
84	}
rt_sched_thread_ready (thread=0x2405ebe0) at rt-thread\src\scheduler_comm.c:116
116	        if (RT_SCHED_CTX(thread).sched_flag_ttmr_set)
123	            error = rt_sched_thread_timer_stop(thread);
rt_sched_thread_timer_stop (thread=0x2405ebe0) at rt-thread\src\scheduler_comm.c:45
45	    if (RT_SCHED_CTX(thread).sched_flag_ttmr_set)
47	        error = rt_timer_stop(&thread->thread_timer);
rt_timer_stop (timer=0x2405ec28) at rt-thread\src\timer.c:632
632	    RT_ASSERT(timer != RT_NULL);
633	    RT_ASSERT(rt_object_get_type(&timer->parent) == RT_Object_Class_Timer);
rt_object_get_type (object=0x2405ec28) at rt-thread\src\object.c:587
587	    RT_ASSERT(object != RT_NULL);
589	    return object->type & ~RT_Object_Class_Static;
590	}
rt_timer_stop (timer=0x2405ec28) at rt-thread\src\timer.c:635
635	    spinlock = _timerlock_idx(timer);
_timerlock_idx (timer=0x2405ec28) at rt-thread\src\timer.c:102
102	    if (timer->parent.flag & RT_TIMER_FLAG_SOFT_TIMER)
109	        return &_htimer_lock;
112	}
rt_timer_stop (timer=0x2405ec28) at rt-thread\src\timer.c:637
637	    level = rt_spin_lock_irqsave(spinlock);
rt_spin_lock_irqsave (lock=0x2405e044 <_htimer_lock>) at rt-thread\src\cpu_up.c:67
67	    level = rt_hw_interrupt_disable();
rt_hw_interrupt_disable () at rt-thread\libcpu\arm\cortex-m7/context_gcc.S:39
39	    MRS     r0, PRIMASK
40	    CPSID   I
41	    BX      LR
rt_spin_lock_irqsave (lock=0x2405e044 <_htimer_lock>) at rt-thread\src\cpu_up.c:68
68	    rt_enter_critical();
rt_enter_critical () at rt-thread\src\scheduler_up.c:507
507	    level = rt_hw_interrupt_disable();
rt_hw_interrupt_disable () at rt-thread\libcpu\arm\cortex-m7/context_gcc.S:39
39	    MRS     r0, PRIMASK
40	    CPSID   I
41	    BX      LR
rt_enter_critical () at rt-thread\src\scheduler_up.c:513
513	    rt_scheduler_lock_nest ++;
514	    critical_level = rt_scheduler_lock_nest;
517	    rt_hw_interrupt_enable(level);
rt_hw_interrupt_enable () at rt-thread\libcpu\arm\cortex-m7/context_gcc.S:49
49	    MSR     PRIMASK, r0
50	    BX      LR
rt_enter_critical () at rt-thread\src\scheduler_up.c:519
519	    return critical_level;
520	}
rt_spin_lock_irqsave (lock=0x2405e044 <_htimer_lock>) at rt-thread\src\cpu_up.c:70
70	    return level;
71	}
rt_timer_stop (timer=0x2405ec28) at rt-thread\src\timer.c:639
639	    if (!(timer->parent.flag & RT_TIMER_FLAG_ACTIVATED))
644	    RT_OBJECT_HOOK_CALL(rt_object_put_hook, (&(timer->parent)));
646	    _timer_remove(timer);
_timer_remove (timer=0x2405ec28) at rt-thread\src\timer.c:195
195	    for (i = 0; i < RT_TIMER_SKIP_LIST_LEVEL; i++)
197	        rt_list_remove(&timer->row[i]);
rt_list_remove (n=0x2405ec3c) at rt-thread\include/rtservice.h:91
91	    n->next->prev = n->prev;
92	    n->prev->next = n->next;
94	    n->next = n->prev = n;
95	}
_timer_remove (timer=0x2405ec28) at rt-thread\src\timer.c:195
195	    for (i = 0; i < RT_TIMER_SKIP_LIST_LEVEL; i++)
199	}
rt_timer_stop (timer=0x2405ec28) at rt-thread\src\timer.c:648
648	    timer->parent.flag &= ~RT_TIMER_FLAG_ACTIVATED;
650	    rt_spin_unlock_irqrestore(spinlock, level);
rt_spin_unlock_irqrestore (lock=0x2405e044 <_htimer_lock>, level=1) at rt-thread\src\cpu_up.c:83
83	    RT_SPIN_UNLOCK_DEBUG(lock, critical_level);
84	    rt_exit_critical_safe(critical_level);
rt_exit_critical_safe (critical_level=0) at rt-thread\src\scheduler_up.c:492
492	    rt_exit_critical();
rt_exit_critical () at rt-thread\src\scheduler_up.c:531
531	    level = rt_hw_interrupt_disable();
rt_hw_interrupt_disable () at rt-thread\libcpu\arm\cortex-m7/context_gcc.S:39
39	    MRS     r0, PRIMASK
40	    CPSID   I
41	    BX      LR
rt_exit_critical () at rt-thread\src\scheduler_up.c:533
533	    rt_scheduler_lock_nest --;
534	    if (rt_scheduler_lock_nest <= 0)
549	        rt_hw_interrupt_enable(level);
rt_hw_interrupt_enable () at rt-thread\libcpu\arm\cortex-m7/context_gcc.S:49
49	    MSR     PRIMASK, r0
50	    BX      LR
rt_exit_critical () at rt-thread\src\scheduler_up.c:551
551	}
rt_exit_critical_safe (critical_level=0) at rt-thread\src\scheduler_up.c:493
493	}
rt_spin_unlock_irqrestore (lock=0x2405e044 <_htimer_lock>, level=1) at rt-thread\src\cpu_up.c:85
85	    rt_hw_interrupt_enable(level);
rt_hw_interrupt_enable () at rt-thread\libcpu\arm\cortex-m7/context_gcc.S:49
49	    MSR     PRIMASK, r0
50	    BX      LR
rt_spin_unlock_irqrestore (lock=0x2405e044 <_htimer_lock>, level=1) at rt-thread\src\cpu_up.c:86
86	}
rt_timer_stop (timer=0x2405ec28) at rt-thread\src\timer.c:652
652	    return RT_EOK;
653	}
rt_sched_thread_timer_stop (thread=0x2405ebe0) at rt-thread\src\scheduler_comm.c:50
50	        RT_SCHED_CTX(thread).sched_flag_ttmr_set = 0;
56	    return error;
57	}
rt_sched_thread_ready (thread=0x2405ebe0) at rt-thread\src\scheduler_comm.c:130
130	        if (!error)
133	            rt_list_remove(&RT_THREAD_LIST_NODE(thread));
rt_list_remove (n=0x2405ec0c) at rt-thread\include/rtservice.h:91
91	    n->next->prev = n->prev;
92	    n->prev->next = n->next;
94	    n->next = n->prev = n;
95	}
rt_sched_thread_ready (thread=0x2405ebe0) at rt-thread\src\scheduler_comm.c:140
140	            rt_sched_insert_thread(thread);
rt_sched_insert_thread (thread=0x2405ebe0) at rt-thread\src\scheduler_up.c:377
377	    RT_ASSERT(thread != RT_NULL);
380	    level = rt_hw_interrupt_disable();
rt_hw_interrupt_disable () at rt-thread\libcpu\arm\cortex-m7/context_gcc.S:39
39	    MRS     r0, PRIMASK
40	    CPSID   I
41	    BX      LR
rt_sched_insert_thread (thread=0x2405ebe0) at rt-thread\src\scheduler_up.c:383
383	    if (thread == rt_current_thread)
rt_thread_self () at rt-thread\src\thread.c:367
367	    return rt_cpu_self()->current_thread;
rt_cpu_self () at rt-thread\src\cpu_up.c:95
95	    return &_cpu;
96	}
rt_thread_self () at rt-thread\src\thread.c:382
382	}
rt_sched_insert_thread (thread=0x2405ebe0) at rt-thread\src\scheduler_up.c:390
390	    RT_SCHED_CTX(thread).stat = RT_THREAD_READY | (RT_SCHED_CTX(thread).stat & ~RT_THREAD_STAT_MASK);
392	    if((RT_SCHED_CTX(thread).stat & RT_THREAD_STAT_YIELD_MASK) != 0)
400	        rt_list_insert_after(&(rt_thread_priority_table[RT_SCHED_PRIV(thread).current_priority]),
rt_list_insert_after (l=0x2405df74 <rt_thread_priority_table+80>, n=0x2405ec0c) at rt-thread\include/rtservice.h:63
63	    l->next->prev = n;
64	    n->next = l->next;
66	    l->next = n;
67	    n->prev = l;
68	}
rt_sched_insert_thread (thread=0x2405ebe0) at rt-thread\src\scheduler_up.c:411
411	    rt_thread_ready_priority_group |= RT_SCHED_PRIV(thread).number_mask;
415	    rt_hw_interrupt_enable(level);
rt_hw_interrupt_enable () at rt-thread\libcpu\arm\cortex-m7/context_gcc.S:49
49	    MSR     PRIMASK, r0
50	    BX      LR
rt_sched_insert_thread (thread=0x2405ebe0) at rt-thread\src\scheduler_up.c:416
416	}
rt_sched_thread_ready (thread=0x2405ebe0) at rt-thread\src\scheduler_comm.c:144
144	    return error;
145	}
rt_thread_resume (thread=0x2405ebe0) at rt-thread\src\thread.c:1026
1026	    if (!error)
1028	        error = rt_sched_unlock_n_resched(slvl);
rt_sched_unlock_n_resched (level=1) at rt-thread\src\scheduler_up.c:132
132	    if (rt_thread_self())
rt_thread_self () at rt-thread\src\thread.c:367
367	    return rt_cpu_self()->current_thread;
rt_cpu_self () at rt-thread\src\cpu_up.c:95
95	    return &_cpu;
96	}
rt_thread_self () at rt-thread\src\thread.c:382
382	}
rt_sched_unlock_n_resched (level=1) at rt-thread\src\scheduler_up.c:135
135	        rt_schedule();
rt_schedule () at rt-thread\src\scheduler_up.c:207
207	    struct rt_thread *curr_thread = rt_thread_self();
rt_thread_self () at rt-thread\src\thread.c:367
367	    return rt_cpu_self()->current_thread;
rt_cpu_self () at rt-thread\src\cpu_up.c:95
95	    return &_cpu;
96	}
rt_thread_self () at rt-thread\src\thread.c:382
382	}
rt_schedule () at rt-thread\src\scheduler_up.c:210
210	    level = rt_hw_interrupt_disable();
rt_hw_interrupt_disable () at rt-thread\libcpu\arm\cortex-m7/context_gcc.S:39
39	    MRS     r0, PRIMASK
40	    CPSID   I
41	    BX      LR
rt_schedule () at rt-thread\src\scheduler_up.c:213
213	    if (rt_scheduler_lock_nest == 0)
323	    rt_hw_interrupt_enable(level);
rt_hw_interrupt_enable () at rt-thread\libcpu\arm\cortex-m7/context_gcc.S:49
49	    MSR     PRIMASK, r0
50	    BX      LR
rt_schedule () at rt-thread\src\scheduler_up.c:326
326	    return;
327	}
rt_sched_unlock_n_resched (level=1) at rt-thread\src\scheduler_up.c:137
137	    rt_hw_interrupt_enable(level);
rt_hw_interrupt_enable () at rt-thread\libcpu\arm\cortex-m7/context_gcc.S:49
49	    MSR     PRIMASK, r0
50	    BX      LR
rt_sched_unlock_n_resched (level=1) at rt-thread\src\scheduler_up.c:139
139	    return RT_EOK;
140	}
rt_thread_resume (thread=0x2405ebe0) at rt-thread\src\thread.c:1034
1034	        if (error == -RT_ESCHEDLOCKED)
1044	    RT_OBJECT_HOOK_CALL(rt_thread_resume_hook, (thread));
1046	    return error;
1047	}
rt_completion_wakeup_by_errno (completion=0x2405593c <spi_bus_obj+520>, thread_errno=-1) at rt-thread\components\drivers\ipc\completion_up.c:209
209	        if (error)
221	    completion->susp_thread_n_flag = RT_COMPLETION_NEW_STAT(RT_NULL, RT_COMPLETED);
223	    rt_spin_unlock_irqrestore(&_completion_lock, level);
rt_spin_unlock_irqrestore (lock=0x2405c0a8 <_completion_lock>, level=1) at rt-thread\src\cpu_up.c:83
83	    RT_SPIN_UNLOCK_DEBUG(lock, critical_level);
84	    rt_exit_critical_safe(critical_level);
rt_exit_critical_safe (critical_level=0) at rt-thread\src\scheduler_up.c:492
492	    rt_exit_critical();
rt_exit_critical () at rt-thread\src\scheduler_up.c:531
531	    level = rt_hw_interrupt_disable();
rt_hw_interrupt_disable () at rt-thread\libcpu\arm\cortex-m7/context_gcc.S:39
39	    MRS     r0, PRIMASK
40	    CPSID   I
41	    BX      LR
rt_exit_critical () at rt-thread\src\scheduler_up.c:533
533	    rt_scheduler_lock_nest --;
534	    if (rt_scheduler_lock_nest <= 0)
536	        rt_scheduler_lock_nest = 0;
538	        rt_hw_interrupt_enable(level);
rt_hw_interrupt_enable () at rt-thread\libcpu\arm\cortex-m7/context_gcc.S:49
49	    MSR     PRIMASK, r0
50	    BX      LR
rt_exit_critical () at rt-thread\src\scheduler_up.c:540
540	        if (rt_current_thread)
rt_thread_self () at rt-thread\src\thread.c:367
367	    return rt_cpu_self()->current_thread;
rt_cpu_self () at rt-thread\src\cpu_up.c:95
95	    return &_cpu;
96	}
rt_thread_self () at rt-thread\src\thread.c:382
382	}
rt_exit_critical () at rt-thread\src\scheduler_up.c:543
543	            rt_schedule();
rt_schedule () at rt-thread\src\scheduler_up.c:207
207	    struct rt_thread *curr_thread = rt_thread_self();
rt_thread_self () at rt-thread\src\thread.c:367
367	    return rt_cpu_self()->current_thread;
rt_cpu_self () at rt-thread\src\cpu_up.c:95
95	    return &_cpu;
96	}
rt_thread_self () at rt-thread\src\thread.c:382
382	}
rt_schedule () at rt-thread\src\scheduler_up.c:210
210	    level = rt_hw_interrupt_disable();
rt_hw_interrupt_disable () at rt-thread\libcpu\arm\cortex-m7/context_gcc.S:39
39	    MRS     r0, PRIMASK
40	    CPSID   I
41	    BX      LR
rt_schedule () at rt-thread\src\scheduler_up.c:213
213	    if (rt_scheduler_lock_nest == 0)
217	        if (rt_thread_ready_priority_group != 0)
220	            int need_insert_from_thread = 0;
222	            to_thread = _scheduler_get_highest_priority_thread(&highest_ready_priority);
_scheduler_get_highest_priority_thread (highest_prio=0x240010b8) at rt-thread\src\scheduler_up.c:100
100	    highest_ready_priority = __rt_ffs(rt_thread_ready_priority_group) - 1;
__rt_ffs (value=1024) at rt-thread\libcpu\arm\cortex-m7\cpuport.c:519
519	    return __builtin_ffs(value);
520	}
_scheduler_get_highest_priority_thread (highest_prio=0x240010b8) at rt-thread\src\scheduler_up.c:104
104	    highest_priority_thread = RT_THREAD_LIST_NODE_ENTRY(rt_thread_priority_table[highest_ready_priority].next);
106	    *highest_prio = highest_ready_priority;
108	    return highest_priority_thread;
109	}
rt_schedule () at rt-thread\src\scheduler_up.c:224
224	            if ((RT_SCHED_CTX(curr_thread).stat & RT_THREAD_STAT_MASK) == RT_THREAD_RUNNING)
226	                if (RT_SCHED_PRIV(curr_thread).current_priority < highest_ready_priority)
230	                else if (RT_SCHED_PRIV(curr_thread).current_priority == highest_ready_priority
237	                    need_insert_from_thread = 1;
241	            if (to_thread != curr_thread)
244	                rt_current_priority = (rt_uint8_t)highest_ready_priority;
245	                from_thread                   = curr_thread;
246	                rt_cpu_self()->current_thread = to_thread;
rt_cpu_self () at rt-thread\src\cpu_up.c:95
95	    return &_cpu;
96	}
rt_schedule () at rt-thread\src\scheduler_up.c:248
248	                RT_OBJECT_HOOK_CALL(rt_scheduler_hook, (from_thread, to_thread));
250	                if (need_insert_from_thread)
252	                    rt_sched_insert_thread(from_thread);
rt_sched_insert_thread (thread=0x2405cc6c <idle_thread>) at rt-thread\src\scheduler_up.c:377
377	    RT_ASSERT(thread != RT_NULL);
380	    level = rt_hw_interrupt_disable();
rt_hw_interrupt_disable () at rt-thread\libcpu\arm\cortex-m7/context_gcc.S:39
39	    MRS     r0, PRIMASK
40	    CPSID   I
41	    BX      LR
rt_sched_insert_thread (thread=0x2405cc6c <idle_thread>) at rt-thread\src\scheduler_up.c:383
383	    if (thread == rt_current_thread)
rt_thread_self () at rt-thread\src\thread.c:367
367	    return rt_cpu_self()->current_thread;
rt_cpu_self () at rt-thread\src\cpu_up.c:95
95	    return &_cpu;
96	}
rt_thread_self () at rt-thread\src\thread.c:382
382	}
rt_sched_insert_thread (thread=0x2405cc6c <idle_thread>) at rt-thread\src\scheduler_up.c:390
390	    RT_SCHED_CTX(thread).stat = RT_THREAD_READY | (RT_SCHED_CTX(thread).stat & ~RT_THREAD_STAT_MASK);
392	    if((RT_SCHED_CTX(thread).stat & RT_THREAD_STAT_YIELD_MASK) != 0)
400	        rt_list_insert_after(&(rt_thread_priority_table[RT_SCHED_PRIV(thread).current_priority]),
rt_list_insert_after (l=0x2405e01c <rt_thread_priority_table+248>, n=0x2405cc98 <idle_thread+44>) at rt-thread\include/rtservice.h:63
63	    l->next->prev = n;
64	    n->next = l->next;
66	    l->next = n;
67	    n->prev = l;
68	}
rt_sched_insert_thread (thread=0x2405cc6c <idle_thread>) at rt-thread\src\scheduler_up.c:411
411	    rt_thread_ready_priority_group |= RT_SCHED_PRIV(thread).number_mask;
415	    rt_hw_interrupt_enable(level);
rt_hw_interrupt_enable () at rt-thread\libcpu\arm\cortex-m7/context_gcc.S:49
49	    MSR     PRIMASK, r0
50	    BX      LR
rt_sched_insert_thread (thread=0x2405cc6c <idle_thread>) at rt-thread\src\scheduler_up.c:416
416	}
rt_schedule () at rt-thread\src\scheduler_up.c:255
255	                if ((RT_SCHED_CTX(from_thread).stat & RT_THREAD_STAT_YIELD_MASK) != 0)
260	                rt_sched_remove_thread(to_thread);
rt_sched_remove_thread (thread=0x2405ebe0) at rt-thread\src\scheduler_up.c:429
429	    RT_ASSERT(thread != RT_NULL);
432	    level = rt_hw_interrupt_disable();
rt_hw_interrupt_disable () at rt-thread\libcpu\arm\cortex-m7/context_gcc.S:39
39	    MRS     r0, PRIMASK
40	    CPSID   I
41	    BX      LR
rt_sched_remove_thread (thread=0x2405ebe0) at rt-thread\src\scheduler_up.c:439
439	    rt_list_remove(&RT_THREAD_LIST_NODE(thread));
rt_list_remove (n=0x2405ec0c) at rt-thread\include/rtservice.h:91
91	    n->next->prev = n->prev;
92	    n->prev->next = n->next;
94	    n->next = n->prev = n;
95	}
rt_sched_remove_thread (thread=0x2405ebe0) at rt-thread\src\scheduler_up.c:440
440	    if (rt_list_isempty(&(rt_thread_priority_table[RT_SCHED_PRIV(thread).current_priority])))
rt_list_isempty (l=0x2405df74 <rt_thread_priority_table+80>) at rt-thread\include/rtservice.h:103
103	    return l->next == l;
104	}
rt_sched_remove_thread (thread=0x2405ebe0) at rt-thread\src\scheduler_up.c:449
449	        rt_thread_ready_priority_group &= ~RT_SCHED_PRIV(thread).number_mask;
454	    rt_hw_interrupt_enable(level);
rt_hw_interrupt_enable () at rt-thread\libcpu\arm\cortex-m7/context_gcc.S:49
49	    MSR     PRIMASK, r0
50	    BX      LR
rt_sched_remove_thread (thread=0x2405ebe0) at rt-thread\src\scheduler_up.c:455
455	}
rt_schedule () at rt-thread\src\scheduler_up.c:261
261	                RT_SCHED_CTX(to_thread).stat = RT_THREAD_RUNNING | (RT_SCHED_CTX(to_thread).stat & ~RT_THREAD_STAT_MASK);
271	                RT_SCHEDULER_STACK_CHECK(to_thread);
rt_scheduler_stack_check (thread=0x2405ebe0) at rt-thread\src\scheduler_comm.c:230
230	    RT_ASSERT(thread != RT_NULL);
249	    if (*((rt_uint8_t *)thread->stack_addr) != '#' ||
251	        (rt_uintptr_t)thread->sp <= (rt_uintptr_t)thread->stack_addr ||
249	    if (*((rt_uint8_t *)thread->stack_addr) != '#' ||
252	        (rt_uintptr_t)thread->sp >
253	        (rt_uintptr_t)thread->stack_addr + (rt_uintptr_t)thread->stack_size)
251	        (rt_uintptr_t)thread->sp <= (rt_uintptr_t)thread->stack_addr ||
274	    else if ((rt_uintptr_t)thread->sp <= ((rt_uintptr_t)thread->stack_addr + 32))
rt_schedule () at rt-thread\src\scheduler_up.c:273
273	                if (rt_interrupt_nest == 0)
277	                    RT_OBJECT_HOOK_CALL(rt_scheduler_switch_hook, (from_thread));
279	                    rt_hw_context_switch((rt_uintptr_t)&from_thread->sp,
280	                            (rt_uintptr_t)&to_thread->sp);
279	                    rt_hw_context_switch((rt_uintptr_t)&from_thread->sp,
rt_hw_context_switch_interrupt () at rt-thread\libcpu\arm\cortex-m7/context_gcc.S:65
65	    LDR     r2, =rt_thread_switch_interrupt_flag
66	    LDR     r3, [r2]
67	    CMP     r3, #1
68	    BEQ     _reswitch
_reswitch () at rt-thread\libcpu\arm\cortex-m7/context_gcc.S:76
76	    LDR     r2, =rt_interrupt_to_thread     /* set rt_interrupt_to_thread */
77	    STR     r1, [r2]
79	    LDR r0, =NVIC_INT_CTRL              /* trigger the PendSV exception (causes context switch) */
80	    LDR r1, =NVIC_PENDSVSET
81	    STR r1, [r0]
82	    BX  LR
rt_schedule () at rt-thread\src\scheduler_up.c:283
283	                    rt_hw_interrupt_enable(level);
rt_hw_interrupt_enable () at rt-thread\libcpu\arm\cortex-m7/context_gcc.S:49
49	    MSR     PRIMASK, r0
50	    BX      LR
rt_schedule () at rt-thread\src\scheduler_up.c:326
326	    return;
327	}
rt_exit_critical () at rt-thread\src\scheduler_up.c:551
551	}
rt_exit_critical_safe (critical_level=0) at rt-thread\src\scheduler_up.c:493
493	}
rt_spin_unlock_irqrestore (lock=0x2405c0a8 <_completion_lock>, level=1) at rt-thread\src\cpu_up.c:85
85	    rt_hw_interrupt_enable(level);
rt_hw_interrupt_enable () at rt-thread\libcpu\arm\cortex-m7/context_gcc.S:49
49	    MSR     PRIMASK, r0
50	    BX      LR
rt_spin_unlock_irqrestore (lock=0x2405c0a8 <_completion_lock>, level=1) at rt-thread\src\cpu_up.c:86
86	}
rt_completion_wakeup_by_errno (completion=0x2405593c <spi_bus_obj+520>, thread_errno=-1) at rt-thread\components\drivers\ipc\completion_up.c:225
225	    return error;
226	}
rt_completion_done (completion=0x2405593c <spi_bus_obj+520>) at rt-thread\components\drivers\ipc\completion_comm.c:22
22	}
HAL_SPI_RxCpltCallback (hspi=0x24055734 <spi_bus_obj>) at libraries\HAL_Drivers\drivers\drv_spi.c:1056
1056	}
HAL_SPI_IRQHandler (hspi=0x24055734 <spi_bus_obj>) at libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_spi.c:3044
3044	    return;
3131	}
SPI1_IRQHandler () at libraries\HAL_Drivers\drivers\drv_spi.c:699
699	    rt_hw_interrupt_enable(level);
rt_hw_interrupt_enable () at rt-thread\libcpu\arm\cortex-m7/context_gcc.S:49
49	    MSR     PRIMASK, r0
50	    BX      LR
SPI1_IRQHandler () at libraries\HAL_Drivers\drivers\drv_spi.c:700
700	}
rt_hw_interrupt_enable () at rt-thread\libcpu\arm\cortex-m7/context_gcc.S:50
50	    BX      LR
Continuing.

2. spi_tx_dma

  • DMA1_Stream4_IRQHandler中调用HAL_DMA_IRQHandler, 在HAL_DMA_IRQHandler中调用了SPI_DMATransmitCplt
  • 在SPI_DMATransmitCplt中，判断TxDMA是以非DMA_CIRCULAR初始化的, 于是开启了__HAL_SPI_ENABLE_IT(hspi, SPI_IT_EOT)中断，这个中断使能触发了SPI中断。
Breakpoint 5, DMA1_Stream4_IRQHandler () at libraries\HAL_Drivers\drivers\drv_spi.c:779
779	    rt_base_t level = rt_hw_interrupt_disable();
rt_hw_interrupt_disable () at rt-thread\libcpu\arm\cortex-m7/context_gcc.S:39
39	    MRS     r0, PRIMASK
40	    CPSID   I
41	    BX      LR
DMA1_Stream4_IRQHandler () at libraries\HAL_Drivers\drivers\drv_spi.c:781
781	    HAL_DMA_IRQHandler(&spi_bus_obj[SPI2_INDEX].dma.handle_tx);
HAL_DMA_IRQHandler (hdma=0x24055a48 <spi_bus_obj+788>) at libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dma.c:1212
1212	  __IO uint32_t count = 0U;
1213	  uint32_t timeout = SystemCoreClock / 9600U;
1216	  DMA_Base_Registers  *regs_dma  = (DMA_Base_Registers *)hdma->StreamBaseAddress;
1217	  BDMA_Base_Registers *regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress;
1219	  tmpisr_dma  = regs_dma->ISR;
1220	  tmpisr_bdma = regs_bdma->ISR;
1222	  if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U)  /* DMA1 or DMA2 instance */
1225	    if ((tmpisr_dma & (DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)
1240	    if ((tmpisr_dma & (DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)
1242	      if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != 0U)
1252	    if ((tmpisr_dma & (DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)
1264	    if ((tmpisr_dma & (DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)
1266	      if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != 0U)
1269	        regs_dma->IFCR = DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU);
1272	        if(((((DMA_Stream_TypeDef   *)hdma->Instance)->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0U)
1296	          if((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_CIRC) == 0U)
1299	            ((DMA_Stream_TypeDef   *)hdma->Instance)->CR  &= ~(DMA_IT_HT);
1302	          if(hdma->XferHalfCpltCallback != NULL)
1305	            hdma->XferHalfCpltCallback(hdma);
SPI_DMAHalfTransmitCplt (hdma=0x24055a48 <spi_bus_obj+788>) at libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_spi.c:3426
3426	  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)
3432	  HAL_SPI_TxHalfCpltCallback(hspi);
HAL_SPI_TxHalfCpltCallback (hspi=0x24055940 <spi_bus_obj+524>) at libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_spi.c:3195
3195	}
SPI_DMAHalfTransmitCplt (hdma=0x24055a48 <spi_bus_obj+788>) at libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_spi.c:3434
3434	}
HAL_DMA_IRQHandler (hdma=0x24055a48 <spi_bus_obj+788>) at libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dma.c:1311
1311	    if ((tmpisr_dma & (DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)
1313	      if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != 0U)
1316	        regs_dma->IFCR = DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU);
1318	        if(HAL_DMA_STATE_ABORT == hdma->State)
1345	        if(((((DMA_Stream_TypeDef   *)hdma->Instance)->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0U)
1369	          if((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_CIRC) == 0U)
1372	            ((DMA_Stream_TypeDef   *)hdma->Instance)->CR  &= ~(DMA_IT_TC);
1375	            hdma->State = HAL_DMA_STATE_READY;
1378	            __HAL_UNLOCK(hdma);
1381	          if(hdma->XferCpltCallback != NULL)
1384	            hdma->XferCpltCallback(hdma);
SPI_DMATransmitCplt (hdma=0x24055a48 <spi_bus_obj+788>) at libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_spi.c:3342
3342	  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3344	  if (hspi->State != HAL_SPI_STATE_ABORT)
3346	    if (hspi->hdmatx->Init.Mode == DMA_CIRCULAR)
3357	      __HAL_SPI_ENABLE_IT(hspi, SPI_IT_EOT); /*重点*/
3360	}
HAL_DMA_IRQHandler (hdma=0x24055a48 <spi_bus_obj+788>) at libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dma.c:1391
1391	    if(hdma->ErrorCode != HAL_DMA_ERROR_NONE)
1566	}
DMA1_Stream4_IRQHandler () at libraries\HAL_Drivers\drivers\drv_spi.c:784
784	    rt_hw_interrupt_enable(level);
rt_hw_interrupt_enable () at rt-thread\libcpu\arm\cortex-m7/context_gcc.S:49
49	    MSR     PRIMASK, r0
50	    BX      LR
DMA1_Stream4_IRQHandler () at libraries\HAL_Drivers\drivers\drv_spi.c:785
785	}
rt_completion_wait_flags (completion=0x24055b48 <spi_bus_obj+1044>, timeout=1000, suspend_flag=2) at rt-thread\components\drivers\ipc\completion_up.c:74
74	    RT_DEBUG_SCHEDULER_AVAILABLE(timeout != 0);
Continuing.
  • SPI_DMATransmitCplt函数重点，根据不同的DMA模式，做不同的处理
  • 对于DMA Circula模式，直接执行HAL_SPI_TxCpltCallback回调
  • 对于DMA_Normal模式，开启SPI_IT_EOT中断， 当SPI_IT_EOT中断触发时，执行HAL_SPI_TxCpltCallback回调
static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
{SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;if (hspi->State != HAL_SPI_STATE_ABORT){if (hspi->hdmatx->Init.Mode == DMA_CIRCULAR){
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)hspi->TxCpltCallback(hspi);
#elseHAL_SPI_TxCpltCallback(hspi);
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */}else{/* Enable EOT interrupt */__HAL_SPI_ENABLE_IT(hspi, SPI_IT_EOT);}}
}
  • SPI2_IRQHandler
  • 这个函数主要是执行了HAL_SPI_TxCpltCallback回调函数, 在这个回调函数中执行rt_completion_done
  • rt_completion_done执行了非常多的动作。这个可以不用管。
Breakpoint 2, SPI2_IRQHandler () at libraries\HAL_Drivers\drivers\drv_spi.c:743
743	    rt_base_t level = rt_hw_interrupt_disable();
rt_hw_interrupt_disable () at rt-thread\libcpu\arm\cortex-m7/context_gcc.S:39
39	    MRS     r0, PRIMASK
40	    CPSID   I
41	    BX      LR
SPI2_IRQHandler () at libraries\HAL_Drivers\drivers\drv_spi.c:745
745	    HAL_SPI_IRQHandler(&spi_bus_obj[SPI2_INDEX].handle);
HAL_SPI_IRQHandler (hspi=0x24055940 <spi_bus_obj+524>) at libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_spi.c:2888
2888	  uint32_t itsource = hspi->Instance->IER;
2889	  uint32_t itflag   = hspi->Instance->SR;
2890	  uint32_t trigger  = itsource & itflag;
2891	  uint32_t cfg1     = hspi->Instance->CFG1;
2892	  uint32_t handled  = 0UL;
2894	  HAL_SPI_StateTypeDef State = hspi->State;
2896	  __IO uint16_t *prxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->RXDR));
2900	  if (HAL_IS_BIT_SET(itflag, SPI_FLAG_SUSP) && HAL_IS_BIT_SET(itsource, SPI_FLAG_EOT))
2915	  if (HAL_IS_BIT_CLR(trigger, SPI_FLAG_OVR) && HAL_IS_BIT_CLR(trigger, SPI_FLAG_UDR) && \
2916	      HAL_IS_BIT_SET(trigger, SPI_FLAG_DXP))
2915	  if (HAL_IS_BIT_CLR(trigger, SPI_FLAG_OVR) && HAL_IS_BIT_CLR(trigger, SPI_FLAG_UDR) && \
2924	  if (HAL_IS_BIT_CLR(trigger, SPI_FLAG_OVR) && HAL_IS_BIT_SET(trigger, SPI_FLAG_RXP) && \
2932	  if (HAL_IS_BIT_CLR(trigger, SPI_FLAG_UDR) && HAL_IS_BIT_SET(trigger, SPI_FLAG_TXP) && \
2947	  if (handled != 0UL)
2953	  if (HAL_IS_BIT_SET(trigger, SPI_FLAG_EOT))
2956	    __HAL_SPI_CLEAR_EOTFLAG(hspi);
2957	    __HAL_SPI_CLEAR_TXTFFLAG(hspi);
2958	    __HAL_SPI_CLEAR_SUSPFLAG(hspi);
2961	    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_EOT);
2964	    if (HAL_IS_BIT_CLR(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN))
2997	    SPI_CloseTransfer(hspi);
SPI_CloseTransfer (hspi=0x24055940 <spi_bus_obj+524>) at libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_spi.c:3893
3893	  uint32_t itflag = hspi->Instance->SR;
3895	  __HAL_SPI_CLEAR_EOTFLAG(hspi);
3896	  __HAL_SPI_CLEAR_TXTFFLAG(hspi);
3899	  __HAL_SPI_DISABLE(hspi);
3902	  __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_TXP | SPI_IT_RXP | SPI_IT_DXP | SPI_IT_UDR | SPI_IT_OVR | \
3906	  CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN);
3909	  if (hspi->State != HAL_SPI_STATE_BUSY_RX)
3911	    if ((itflag & SPI_FLAG_UDR) != 0UL)
3919	  if (hspi->State != HAL_SPI_STATE_BUSY_TX)
3941	  if ((itflag & SPI_FLAG_MODF) != 0UL)
3948	  if ((itflag & SPI_FLAG_FRE) != 0UL)
3954	  hspi->TxXferCount = (uint16_t)0UL;
3955	  hspi->RxXferCount = (uint16_t)0UL;
3956	}
HAL_SPI_IRQHandler (hspi=0x24055940 <spi_bus_obj+524>) at libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_spi.c:2999
2999	    hspi->State = HAL_SPI_STATE_READY;
3000	    if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
3026	    if (State == HAL_SPI_STATE_BUSY_TX_RX)
3030	    else if (State == HAL_SPI_STATE_BUSY_RX)
3034	    else if (State == HAL_SPI_STATE_BUSY_TX)
3036	      HAL_SPI_TxCpltCallback(hspi);
HAL_SPI_TxCpltCallback (hspi=0x24055940 <spi_bus_obj+524>) at libraries\HAL_Drivers\drivers\drv_spi.c:1048
1048	    struct stm32_spi *spi_drv =  rt_container_of(hspi, struct stm32_spi, handle);
1049	    rt_completion_done(&spi_drv->cpt);
rt_completion_done (completion=0x24055b48 <spi_bus_obj+1044>) at rt-thread\components\drivers\ipc\completion_comm.c:21
21	    rt_completion_wakeup_by_errno(completion, -1);
rt_completion_wakeup_by_errno (completion=0x24055b48 <spi_bus_obj+1044>, thread_errno=-1) at rt-thread\components\drivers\ipc\completion_up.c:189
189	    RT_ASSERT(completion != RT_NULL);
191	    level = rt_spin_lock_irqsave(&_completion_lock);
rt_spin_lock_irqsave (lock=0x2405c0a8 <_completion_lock>) at rt-thread\src\cpu_up.c:67
67	    level = rt_hw_interrupt_disable();
rt_hw_interrupt_disable () at rt-thread\libcpu\arm\cortex-m7/context_gcc.S:39
39	    MRS     r0, PRIMASK
40	    CPSID   I
41	    BX      LR
rt_spin_lock_irqsave (lock=0x2405c0a8 <_completion_lock>) at rt-thread\src\cpu_up.c:68
68	    rt_enter_critical();
rt_enter_critical () at rt-thread\src\scheduler_up.c:507
507	    level = rt_hw_interrupt_disable();
rt_hw_interrupt_disable () at rt-thread\libcpu\arm\cortex-m7/context_gcc.S:39
39	    MRS     r0, PRIMASK
40	    CPSID   I
41	    BX      LR
rt_enter_critical () at rt-thread\src\scheduler_up.c:513
513	    rt_scheduler_lock_nest ++;
514	    critical_level = rt_scheduler_lock_nest;
517	    rt_hw_interrupt_enable(level);
rt_hw_interrupt_enable () at rt-thread\libcpu\arm\cortex-m7/context_gcc.S:49
49	    MSR     PRIMASK, r0
50	    BX      LR
rt_enter_critical () at rt-thread\src\scheduler_up.c:519
519	    return critical_level;
520	}
rt_spin_lock_irqsave (lock=0x2405c0a8 <_completion_lock>) at rt-thread\src\cpu_up.c:70
70	    return level;
71	}
rt_completion_wakeup_by_errno (completion=0x24055b48 <spi_bus_obj+1044>, thread_errno=-1) at rt-thread\components\drivers\ipc\completion_up.c:192
192	    if (RT_COMPLETION_FLAG(completion) == RT_COMPLETED)
198	    suspend_thread = RT_COMPLETION_THREAD(completion);
199	    if (suspend_thread)
218	        error = -RT_EEMPTY;
221	    completion->susp_thread_n_flag = RT_COMPLETION_NEW_STAT(RT_NULL, RT_COMPLETED);
223	    rt_spin_unlock_irqrestore(&_completion_lock, level);
rt_spin_unlock_irqrestore (lock=0x2405c0a8 <_completion_lock>, level=1) at rt-thread\src\cpu_up.c:83
83	    RT_SPIN_UNLOCK_DEBUG(lock, critical_level);
84	    rt_exit_critical_safe(critical_level);
rt_exit_critical_safe (critical_level=0) at rt-thread\src\scheduler_up.c:492
492	    rt_exit_critical();
rt_exit_critical () at rt-thread\src\scheduler_up.c:531
531	    level = rt_hw_interrupt_disable();
rt_hw_interrupt_disable () at rt-thread\libcpu\arm\cortex-m7/context_gcc.S:39
39	    MRS     r0, PRIMASK
40	    CPSID   I
41	    BX      LR
rt_exit_critical () at rt-thread\src\scheduler_up.c:533
533	    rt_scheduler_lock_nest --;
534	    if (rt_scheduler_lock_nest <= 0)
536	        rt_scheduler_lock_nest = 0;
538	        rt_hw_interrupt_enable(level);
rt_hw_interrupt_enable () at rt-thread\libcpu\arm\cortex-m7/context_gcc.S:49
49	    MSR     PRIMASK, r0
50	    BX      LR
rt_exit_critical () at rt-thread\src\scheduler_up.c:540
540	        if (rt_current_thread)
rt_thread_self () at rt-thread\src\thread.c:367
367	    return rt_cpu_self()->current_thread;
rt_cpu_self () at rt-thread\src\cpu_up.c:95
95	    return &_cpu;
96	}
rt_thread_self () at rt-thread\src\thread.c:382
382	}
rt_exit_critical () at rt-thread\src\scheduler_up.c:543
543	            rt_schedule();
rt_schedule () at rt-thread\src\scheduler_up.c:207
207	    struct rt_thread *curr_thread = rt_thread_self();
rt_thread_self () at rt-thread\src\thread.c:367
367	    return rt_cpu_self()->current_thread;
rt_cpu_self () at rt-thread\src\cpu_up.c:95
95	    return &_cpu;
96	}
rt_thread_self () at rt-thread\src\thread.c:382
382	}
rt_schedule () at rt-thread\src\scheduler_up.c:210
210	    level = rt_hw_interrupt_disable();
rt_hw_interrupt_disable () at rt-thread\libcpu\arm\cortex-m7/context_gcc.S:39
39	    MRS     r0, PRIMASK
40	    CPSID   I
41	    BX      LR
rt_schedule () at rt-thread\src\scheduler_up.c:213
213	    if (rt_scheduler_lock_nest == 0)
217	        if (rt_thread_ready_priority_group != 0)
220	            int need_insert_from_thread = 0;
222	            to_thread = _scheduler_get_highest_priority_thread(&highest_ready_priority);
_scheduler_get_highest_priority_thread (highest_prio=0x240010b8) at rt-thread\src\scheduler_up.c:100
100	    highest_ready_priority = __rt_ffs(rt_thread_ready_priority_group) - 1;
__rt_ffs (value=-2147483648) at rt-thread\libcpu\arm\cortex-m7\cpuport.c:519
519	    return __builtin_ffs(value);
520	}
_scheduler_get_highest_priority_thread (highest_prio=0x240010b8) at rt-thread\src\scheduler_up.c:104
104	    highest_priority_thread = RT_THREAD_LIST_NODE_ENTRY(rt_thread_priority_table[highest_ready_priority].next);
106	    *highest_prio = highest_ready_priority;
108	    return highest_priority_thread;
109	}
rt_schedule () at rt-thread\src\scheduler_up.c:224
224	            if ((RT_SCHED_CTX(curr_thread).stat & RT_THREAD_STAT_MASK) == RT_THREAD_RUNNING)
226	                if (RT_SCHED_PRIV(curr_thread).current_priority < highest_ready_priority)
228	                    to_thread = curr_thread;
241	            if (to_thread != curr_thread)
316	                rt_sched_remove_thread(curr_thread);
rt_sched_remove_thread (thread=0x24063400) at rt-thread\src\scheduler_up.c:429
429	    RT_ASSERT(thread != RT_NULL);
432	    level = rt_hw_interrupt_disable();
rt_hw_interrupt_disable () at rt-thread\libcpu\arm\cortex-m7/context_gcc.S:39
39	    MRS     r0, PRIMASK
40	    CPSID   I
41	    BX      LR
rt_sched_remove_thread (thread=0x24063400) at rt-thread\src\scheduler_up.c:439
439	    rt_list_remove(&RT_THREAD_LIST_NODE(thread));
rt_list_remove (n=0x2406342c) at rt-thread\include/rtservice.h:91
91	    n->next->prev = n->prev;
92	    n->prev->next = n->next;
94	    n->next = n->prev = n;
95	}
rt_sched_remove_thread (thread=0x24063400) at rt-thread\src\scheduler_up.c:440
440	    if (rt_list_isempty(&(rt_thread_priority_table[RT_SCHED_PRIV(thread).current_priority])))
rt_list_isempty (l=0x2405dfc4 <rt_thread_priority_table+160>) at rt-thread\include/rtservice.h:103
103	    return l->next == l;
104	}
rt_sched_remove_thread (thread=0x24063400) at rt-thread\src\scheduler_up.c:449
449	        rt_thread_ready_priority_group &= ~RT_SCHED_PRIV(thread).number_mask;
454	    rt_hw_interrupt_enable(level);
rt_hw_interrupt_enable () at rt-thread\libcpu\arm\cortex-m7/context_gcc.S:49
49	    MSR     PRIMASK, r0
50	    BX      LR
rt_sched_remove_thread (thread=0x24063400) at rt-thread\src\scheduler_up.c:455
455	}
rt_schedule () at rt-thread\src\scheduler_up.c:317
317	                RT_SCHED_CTX(curr_thread).stat = RT_THREAD_RUNNING | (RT_SCHED_CTX(curr_thread).stat & ~RT_THREAD_STAT_MASK);
323	    rt_hw_interrupt_enable(level);
rt_hw_interrupt_enable () at rt-thread\libcpu\arm\cortex-m7/context_gcc.S:49
49	    MSR     PRIMASK, r0
50	    BX      LR
rt_schedule () at rt-thread\src\scheduler_up.c:326
326	    return;
327	}
rt_exit_critical () at rt-thread\src\scheduler_up.c:551
551	}
rt_exit_critical_safe (critical_level=0) at rt-thread\src\scheduler_up.c:493
493	}
rt_spin_unlock_irqrestore (lock=0x2405c0a8 <_completion_lock>, level=1) at rt-thread\src\cpu_up.c:85
85	    rt_hw_interrupt_enable(level);
rt_hw_interrupt_enable () at rt-thread\libcpu\arm\cortex-m7/context_gcc.S:49
49	    MSR     PRIMASK, r0
50	    BX      LR
rt_spin_unlock_irqrestore (lock=0x2405c0a8 <_completion_lock>, level=1) at rt-thread\src\cpu_up.c:86
86	}
rt_completion_wakeup_by_errno (completion=0x24055b48 <spi_bus_obj+1044>, thread_errno=-1) at rt-thread\components\drivers\ipc\completion_up.c:225
225	    return error;
226	}
rt_completion_done (completion=0x24055b48 <spi_bus_obj+1044>) at rt-thread\components\drivers\ipc\completion_comm.c:22
22	}
HAL_SPI_TxCpltCallback (hspi=0x24055940 <spi_bus_obj+524>) at libraries\HAL_Drivers\drivers\drv_spi.c:1050
1050	}
HAL_SPI_IRQHandler (hspi=0x24055940 <spi_bus_obj+524>) at libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_spi.c:3044
3044	    return;
3131	}
SPI2_IRQHandler () at libraries\HAL_Drivers\drivers\drv_spi.c:748
748	    rt_hw_interrupt_enable(level);
rt_hw_interrupt_enable () at rt-thread\libcpu\arm\cortex-m7/context_gcc.S:49
49	    MSR     PRIMASK, r0
50	    BX      LR
SPI2_IRQHandler () at libraries\HAL_Drivers\drivers\drv_spi.c:749
749	}
rt_completion_wait_flags (completion=0x24055b48 <spi_bus_obj+1044>, timeout=1000, suspend_flag=2) at rt-thread\components\drivers\ipc\completion_up.c:74
74	    RT_DEBUG_SCHEDULER_AVAILABLE(timeout != 0);
http://www.dtcms.com/a/353973.html

相关文章：

  • Rust 登堂 之 迭代器Iterator（三）
  • 如何构建灵活、可控、可扩展的多云网络底座
  • 【高级机器学习】1. Hypothesis 与 Objective Function
  • solidworks2024保姆级安装教程及解锁版安装包下载！
  • 【编号478】美国土地利用数据本土、阿拉斯加、夏威夷岛土地利用数据
  • 蛋白质残基 - 残基距离计算：单蛋白工具与批量处理方案
  • 【目标检测】论文阅读5
  • 记录一次内存问题排查
  • 比赛竞猜算法设计思路
  • MySQL InnoDB vs MyISAM
  • 【系统分析师】高分论文：论信息系统开发方法及应用
  • 前端漏洞（下）- 会话固定漏洞
  • Databend 亮相 DTCC 2025：存算分离架构引领湖仓一体化
  • 漫谈《数字图像处理》之霍夫变换
  • 一文辨析编程语言的强类型与弱类型、静态类型与动态类型
  • 【Java知识】Java线程相关对象全面解析与最佳实践
  • 吴恩达机器学习（一）
  • 盲埋孔在那里下单？猎板PCB盲埋孔制造优势
  • vue3 之异步轮训 hook 封装
  • 深度解析BiTGAN：基于双向Transformer生成对抗网络的长期人体动作预测
  • S 3.1深度学习--卷积神经网络
  • JavaScript工厂模式
  • 鸿蒙、安卓系统如何体验谷歌服务？实用方法分享
  • LangGraph - API多种访问方式
  • Docker 入门指南：从基础概念到常见命令及高级工具详解
  • Transformer 模型详解
  • [Sync_ai_vid] 唇形同步评判器 | 图像与视频处理器 | GPU测试
  • 为什么 “int ” 会变成 “int”？C++ 引用折叠的原理与本质详解
  • nacos2.4.1版本开启鉴权
  • SmartMediakit视角构建低空经济的超低延迟视频基础设施