9-DS18B20-verilog驱动

DS18B20-verilog驱动

1.

module ds18b20_dri1(input              clk        ,         // 时钟信号（50MHz）input              rst_n      ,         // 复位信号inout              dq         ,         // DS18B20的DQ引脚数据output reg [19:0]  temp_data  ,         // 转换后得到的温度值output reg         sign                 // 符号位
);localparam  ROM_SKIP_CMD        = 8'hCC;           // 跳过 ROM 命令
localparam  CONVERT_CMD         = 8'h44;           // 温度转换命令
localparam  READ_TEMP_CMD       = 8'hbe;           // 读 DS1820 温度暂存器命令reg     [ 4:0]         cnt         ;        // 分频计数器
reg                    clk_1us     ;        // 1MHz时钟
reg     [19:0]         cnt_1us     ;        // 微秒计数
//
reg     [ 3:0]         flow_cnt    ;        // 流转计数
reg                    flow_cnt_ok ;        // 流转计数
reg     [ 2:0]         order_cnt    ;       // 命令计数
reg     [ 3:0]         wr_cnt      ;        // 写计数
reg     [ 4:0]         rd_cnt      ;        // 读计数.
reg                    rest_ok     ;        // 复位OK
//
reg     [ 7:0]         wr_data     ;        // 写入DS18B20的数据
//
reg     [15:0]         rd_data     ;        // 采集到的数据
reg     [15:0]         org_data    ;        // 读取到的原始温度数据
reg     [10:0]         data1       ;        // 对原理温度进行符号处理
reg                    cnt_1us_en  ;        // 使能计时
reg                    dq_out      ;        // DS18B20的dq输出//wire define
wire    [19:0]         data2       ;        // 对处理后的进行转换处理//*****************************************************
//**                    main code
//*****************************************************
assign dq = dq_out;always @ (posedge clk or negedge rst_n) begin//实现1us的分频if (!rst_n) begincnt     <= 5'b0;clk_1us <= 1'b0;endelse if(cnt < 5'd24) begincnt     <= cnt + 1'b1;clk_1us <= clk_1us;endelse begincnt     <= 5'b0;clk_1us <= ~clk_1us;end
end
///////////////////////////////////////////////////////////////
always @ (posedge clk_1us or negedge rst_n) beginif (!rst_n)cnt_1us <= 20'b0;else if (cnt_1us_en)cnt_1us <= cnt_1us + 1'b1;elsecnt_1us <= 20'b0;
end
/////////////////////////////////////////////////////////////////
/*
0复位
1加载CC
2写字节
3加载44
4写字节
5延时
6复位
7加载CC
8写写字节
9加BE
10写字节
11读温度
*/
always @ (posedge clk_1us or negedge rst_n) beginif (!rst_n)begin rest_ok<= 1'b0;flow_cnt_ok<= 1'b0;order_cnt<= 3'b0;cnt_1us_en<= 1'b0;flow_cnt<=5'd0;dq_out  <=  1'bZ;wr_data<=8'd0;rd_data<=16'd0;wr_cnt<=4'd0;rd_cnt<=5'd0;org_data<=16'd0;end //else if (flow_cnt_ok)begin flow_cnt<=((flow_cnt>=5'd12)? (1'b0):(flow_cnt+1'b1));//状态技术+1flow_cnt_ok<= 1'b0;end //else if (flow_cnt==5'd0||flow_cnt==5'd6)begincnt_1us_en<= 1'b1;//开始计时if (cnt_1us <= 20'd500)dq_out <= 1'b0;else if (cnt_1us == 20'd501)dq_out <= 1'bz;else if (cnt_1us <= 20'd1000)begin if(!dq) rest_ok	<= 1'b1;end else if(rest_ok==1'b1)begin flow_cnt_ok<= 1'b1;cnt_1us_en<= 1'b0;//停止计时rest_ok<= 1'b0;end	else begin cnt_1us_en<= 1'b0;//停止计时end end//else if (flow_cnt==5'd1||flow_cnt==5'd7)begin wr_data <= ROM_SKIP_CMD;flow_cnt_ok<= 1'b1;end//else if (flow_cnt==5'd3)beginwr_data <= CONVERT_CMD;flow_cnt_ok<= 1'b1;end//else if (flow_cnt==5'd9)beginwr_data <= READ_TEMP_CMD;flow_cnt_ok<= 1'b1;end//写字节else if (flow_cnt==5'd2||flow_cnt==5'd4||flow_cnt==5'd8||flow_cnt==5'd10)begin if(wr_cnt<= 4'd7)begincnt_1us_en<= 1'b1;//开始计时 if (cnt_1us <= 20'd0)//拉低1usdq_out <= 1'b0;//信号线拉低 else if (cnt_1us <= 20'd60)dq_out <= wr_data[wr_cnt];//从地位开始发送数据else if (cnt_1us <= 20'd79)dq_out <= 1'bz;		//释放总线（发送间隔）else if (cnt_1us == 20'd80)//////////////////////guanjianwr_cnt<=wr_cnt+1'b1;else begincnt_1us_en<= 1'b0;//停止计时endendelse beginwr_cnt <= 4'b0;cnt_1us_en<= 1'b0;//停止计时flow_cnt_ok<= 1'b1;endend  //延时else if (flow_cnt==5'd5)begincnt_1us_en<= 1'b1;//开始计时if (cnt_1us >= 20'd10000)begincnt_1us_en<= 1'b0;flow_cnt_ok<= 1'b1;end end//读字节else if (flow_cnt==5'd11)begin//读数据if(rd_cnt < 5'd16)begincnt_1us_en <= 1'b1;if (cnt_1us <= 20'd1)//拉低1usdq_out <= 1'b0;//信号线拉低else if (cnt_1us <= 20'd13)dq_out <= 1'bz;//信号线拉低else if (cnt_1us == 20'd14)beginrd_data <= {dq,rd_data[15:1]}; endelse if (cnt_1us <= 20'd64) begindq_out <= 1'bz;//信号线拉低rd_cnt<=rd_cnt+1'b1;endelse cnt_1us_en<=1'b0;endelse beginrd_cnt <= 5'd0;cnt_1us_en<= 1'b0;//停止计时flow_cnt_ok<= 1'b1;org_data  <= rd_data;endendelse if (flow_cnt==5'd12)begincnt_1us_en<= 1'b1;//开始计时if (cnt_1us >= 20'd100000)begincnt_1us_en<= 1'b0;flow_cnt_ok<= 1'b1;end end
end
//
always @(posedge clk_1us or negedge rst_n) beginif(!rst_n) beginsign  <=  1'b0;data1 <= 11'b0;endelse if(org_data[15] == 1'b0) beginsign  <= 1'b0;data1 <= org_data[10:0];endelse if(org_data[15] == 1'b1) beginsign  <= 1'b1;data1 <= ~org_data[10:0] + 1'b1;end
end/////////////////////////////////////////////
assign data2 = (data1 * 11'd625)/ 7'd100;/////////////////////////////////////////////
always @(posedge clk_1us or negedge rst_n) beginif(!rst_n)temp_data <= 20'b0;elsetemp_data <= data2;
endendmodule