arinc818_icd设计范例

module arinc818_icd
(
input gt_clk,
input gt_rstn,

input advb_frame_last,//0:non-last;1:frame last
input[31:0]container_cnt,
input[31:0]advb_Frame_cnt,

);

//---------------------------------
//界定符
always@(posedge gt_clk)begin
SOFi                          <=  {K28_5,D21_5,D22_2,D22_2};//
SOFn                         <=  {K28_5,D21_5,D22_1,D22_1};//
EOFn                         <=  {K28_5,D21_4,D21_6,D21_6};//
EOFt                         <=  {K28_5,D21_4,D21_3,D21_3};//
end

//IDLE空闲字符
always@(posedge gt_clk)begin
ADVB_IDLE                    <=  32'hBC95_B5B5;
end

//ADVB FRAME HEADER:6 words
always@(posedge gt_clk)begin
frame_WORDS0           <=8'h44            ; //R_CTL           
frame_WORDS0           <=24'h00_0000      ; //DST_ID       
frame_WORDS1[7:0]      <=8'h00            ; //CS_CTL         
frame_WORDS1[32:8]     <=24'h00_0000      ;  //SRC_ID   
frame_WORDS2           <=8'h61            ; //TYPE          
frame_WORDS2           <={4'h03,advb_frame_last,19'd0};//F_CTL:  0x30 or 0x38 
frame_WORDS3           <=Container_cnt    ;//SEQ_ID容器计数低位     
frame_WORDS3           <=8'h00            ;//DF_CTL      
frame_WORDS3           <=advb_Frame_cnt   ;//ADVB帧计数:SEQ_CNT
frame_WORDS4             <=32'hffff_ffff    ;//OX_RX_ID       
frame_WORDS5           <=32'h0000_0000    ;//Parameter
end


//container header:22 words
always@(posedge gt_clk)begin
container_WORDS0         <=Container_cnt    ;//output reg [31:0] 容器计数 
container_WORDS1         <= ;
container_WORDS2         <= ;
container_WORDS3         <= ;
container_WORDS4         <= ;
container_WORDS5         <= ;
container_WORDS6         <= ;
container_WORDS7         <= ;
container_WORDS8         <= ;
container_WORDS9         <= ;
container_WORDS10         <= ;
container_WORDS11         <= ;
container_WORDS12         <= ;
container_WORDS13         <= ;
container_WORDS14         <= ;
container_WORDS15         <= ;
container_WORDS16         <= ;
container_WORDS17         <= ;
container_WORDS18         <= ;
container_WORDS19         <= ;
container_WORDS20         <= ;
container_WORDS21         <= ;
end

//object0辅助数据：4 words

always@(posedge gt_clk)begin
object0_words0 <= {rows,cols};
object0_words1 <= {CI,P,PA,PAO,PTN,BITS_A,BITS_B,BITS_C,BITS_D};
object0_words2 <= {PROR_CRC};
object0_words3 <= {pam2_type,pam2_data,pam1_type,pam1_data};
end
//--------------------------------

endmodule