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FPGA学习笔记_李敏儿oc的博客-CSDN博客
TLV5618.v：实现DAC数模转换，产生模拟信号，输出指定电压值
时序图
FPGA学习笔记：数据采集传输系统设计（二）：TLV5618型DAC驱动-CSDN博客
ADC128S052.v：实现ADC模数转换，将采集到的模拟信号转换为12位数字信号，实现单次AD采集
FIFO存储器：调用Quartus II自带的FIFO IP核，用于存储连续ADC采样的数据
FPGA学习笔记：数据采集传输系统设计（四）：FIFO IP核调用与仿真波形解读_fpga dma传输来自fifo的数据-CSDN博客
UART串口：包含串口发送和串口接收，用于实现串口通信
ADC_FIFO.v：调用ADC128S052.v，实现连续AD采样，并将采样数据存储至FIFO存储器
module adc_fifo(input Clk, //系统时钟input Rst_n, //系统复位input Start, //开始采集标志位output reg AD_Done, //采集完成标志位input wire ADC_OUT, //ADC串行数字信号output wire ADC_CS_N, //ADC片选output wire ADC_DIN, //串行数据送给ADC芯片output wire ADC_SCLK, //ADC时钟output wire ADC_Done, //单次AD采集完成标志位，仿真时使用input full, //FIFO满标志位output reg wrreq, //FIFO写使能output reg [11:0] FIFO_DATA //FIFO数据输入
);parameter ADC_Cnt_MAX = 11'd128; //AD采集次数/*****模块间信号连线*****/ reg ADC_Start; //单次AD采集开始标志位wire [11:0] ADC_DATA; //单次AD采集数据/*****本模块内部寄存器、参数定义*****/ reg ADC_State; //连续采集状态reg [10:0] ADC_Cnt; //采集128次计数器reg [2:0] state;localparam IDLE = 3'b001, //空闲状态WAIT_ADC_DONE = 3'b010, //等待单次AD采集完成WRITE_FIFO = 3'b100; //延时一拍，数据写入FIFOalways@(posedge Clk or negedge Rst_n)if(!Rst_n) beginADC_Cnt <= 11'd0;ADC_Start <= 1'b0;wrreq <= 1'b0;FIFO_DATA <= 12'd0;state <= IDLE;endelse begincase(state)IDLE:if(ADC_State) beginADC_Start <= 1'b1;//开启单次AD采集state <= WAIT_ADC_DONE;endelsestate <= IDLE;WAIT_ADC_DONE:beginADC_Start <= 1'b0;if(ADC_Done == 1'b1) begin//等待AD采集完成FIFO_DATA <= ADC_DATA;wrreq = 1'b1;ADC_Cnt <= ADC_Cnt + 1'b1;state <= WRITE_FIFO;endelsestate <= WAIT_ADC_DONE;endWRITE_FIFO:beginwrreq = 1'b0;if(ADC_Cnt == ADC_Cnt_MAX)ADC_Cnt <= 11'd0;state <= IDLE;enddefault:state <= IDLE;endcaseendalways@(posedge Clk or negedge Rst_n)if(!Rst_n)AD_Done <= 1'b0;else if(ADC_Cnt == ADC_Cnt_MAX)AD_Done <= 1'b1;else AD_Done <= 1'b0;always@(posedge Clk or negedge Rst_n)if(!Rst_n)ADC_State <= 1'b0;else if(Start)ADC_State <= 1'b1;else if(ADC_Cnt == ADC_Cnt_MAX)ADC_State <= 1'b0;//ADC采集模块adc128s052 adc1(.Clk(Clk),.Rst_n(Rst_n),.DATA(ADC_DATA), //并行数字信号.Channel(3'd6), //通道选择.Start(ADC_Start), //开始标志位.Conv_done(ADC_Done),//完成标志位.ADC_CS_N(ADC_CS_N), //片选.ADC_DIN(ADC_DIN), //串行数据送给ADC芯片.ADC_SCLK(ADC_SCLK), //ADC时钟.ADC_OUT(ADC_OUT) //串行数字信号);defparam adc1.DIV_PARAM = 8;//ADC时钟50/8 = 6.25Mhz
endmoduleFIFO_UART.v：从FIFO中读取转换后的数字信号，并将其通过UART发送至PC端
module fifo_uart_tx(input Clk, //系统时钟input Rst_n, //系统复位input Start, //开始发送数据标志位input empty, //FIFO空标志位input [11:0] FIFO_Q, //FIFO数据输入output reg rdreq, //FIFO读使能output reg Uart_done, //所有数据发送完毕output wire uart_tx //串口数据发送端
);parameter UART_Cnt_MAX = 11'd128; //发送数据个数/*****模块间信号连线*****/ reg send_en; //单次发送使能reg [7:0] send_data; //单次发送数据wire tx_done; //单次发送结束标志/*****本模块内部寄存器、参数定义*****/ reg [10:0] UART_Cnt; //发送128次计数器reg [4:0] state;localparamIDLE = 5'b00001, //空闲状态DELY = 5'b00010, //空一拍延时，等待FIFO_Q数据更新SEND_HIGH = 5'b00100, //发送ADC高四位数据SEND_LOW = 5'b01000, //发送ADC低八位数据WAIT_SEND_DONE = 5'b10000; //等待发送结束always@(posedge Clk or negedge Rst_n)if(!Rst_n) beginrdreq <= 1'b0;send_en <= 1'b0;send_data <= 8'd0;UART_Cnt <= 11'd0;state <= IDLE;endelse begincase(state)IDLE:if(empty == 1'b1) beginif(UART_Cnt == UART_Cnt_MAX)UART_Cnt <= 11'd0;state <= IDLE;endelse beginrdreq <= 1'b1;state <= DELY;endDELY:begin//空一拍延时，此状态FIFO_Q数据更新rdreq <= 1'b0;state <= SEND_HIGH;endSEND_HIGH:beginsend_en <= 1'b1;send_data <= {4'd0,FIFO_Q[11:8]};//发送ADC高四位state <= SEND_LOW;endSEND_LOW:beginif(tx_done)begin//等待发送完成send_en <= 1'b1;send_data <= FIFO_Q[7:0];//发送ADC低八位state <= WAIT_SEND_DONE;endelse beginstate <= SEND_LOW;send_en <= 1'b0;endendWAIT_SEND_DONE:beginif(tx_done) begin//等待发送完成UART_Cnt <= UART_Cnt + 1'b1;state <= IDLE;endelse beginstate <= WAIT_SEND_DONE;send_en <= 1'b0;endenddefault:state <= IDLE; endcaseendalways@(posedge Clk or negedge Rst_n)if(!Rst_n)Uart_done <= 1'b0;else if(UART_Cnt == UART_Cnt_MAX)Uart_done <= 1'b1;elseUart_done <= 1'b0;//串口发送模块uart_data_tx data_tx( .Clk(Clk),.Rst_n(Rst_n),.send_en(send_en),.data(send_data),.baud_set(3'd2), //波特率9600.tx(uart_tx), //数据发送端.tx_done(tx_done));
endmoduleFPGA学习笔记：数据采集传输系统设计（六）：ADC采集FIFO缓存UART发送系统顶层及仿真_fpga adc-CSDN博客