clk_divide时钟分频模块
`timescale 1ns / 1ps
//coding format:ANSI GB2312 GBK
//模块名称：clk_divide
//模块作用：clk_divide
//实现思路：对时钟进行分频
//作者：徐后乐
//时间：2025.04.21
module clk_divide #(
parameter DIVIDE=32'd1000
) (
input wire clk ,
input wire rst_n ,
output reg clk_out
);
reg[31:0] count;
localparam DIVIDE_2=DIVIDE/2;
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
count <='b0;
clk_out <='d0;
end
else
begin
if(count>=(DIVIDE-32'd1))
begin
count <='b0;
end
else
begin
count <=count+'d1;
end
if(count>=DIVIDE_2)
begin
clk_out <=1'b1;
end
else
begin
clk_out <=1'b0;
end
end
end
endmodule