【硬件】Verilog相关

1. 基本代码

1. 在时钟下检测一段电平信号的上升沿

   module level2edge {input clk,input rstn,input D,out pos_Q
   };
   reg D_r;
   reg pos_Q;
   always @(posedge clk or negedge rstn) beginif(!rstn)D_r <= l'b0;elseD_r <= 0
   end
   assign Q = (~D_r)&D;
   always @(posedge clk or negedge rstn) beginif(!rstn)pos_Q <= 'h0else if(Q==1)pos_Q <= 1'h1;elsepos_Q <= 1'h0;
   end
   endmoudle
   

2. FPGA通过纯verilog实现10g万兆UDP协议栈