基于TI的TDA4高速信号仿真条件的理解 4.1 4.2

Application Note
《Jacinto7 AM6x, TDA4x, and DRA8x High-Speed Interface Design Guidelines》

PART 4 Board Design Simulations

This section is intended to provide an overview of the basic system-level board extraction, simulation, and analysis methodologies for high-speed serial interfaces.

本节旨在概述高速串行接口的基本系统级板提取、仿真和分析方法。

This is an essential step to ensure the PCB design meets all the requirements to operate the targeted speeds.
这是确保PCB设计满足所有要求以运行目标速度的重要步骤。
 

4.1 Board Model Extraction 板子模型提取

The board level extraction guidelines listed below are intended to work in any EDA extraction tool and are not tool-specific.

下面列出的板级提取指南适用于任何EDA提取工具，而不是特定于工具的。

It is important to follow the steps outlined in Section 4.2 through Section 4.4 immediately after completing touchstone model extractions.

完成touchstone模型提取后，然后按照第4.2节到4.4节中概述的步骤进行操作是很重要的。

The design should be checked with these steps prior to running IBIS simulations.

在运行IBIS仿真之前，应该用如下步骤检查设计。

• For high speed serial interface extractions, there is no need to extract power and signal nets together in a 3D-EM solver. Simulations are only intended for Signal Integrity.

·对于高速串行接口提取，不需要在3D-EM求解器中同时提取电源和信号nets。仿真仅用于信号完整性分析目的，不需要提取电源部分参数。

• Use wide-band models. It is recommended to extract from DC to at least till 6x the Nyquist frequency (for USB3.1 Gen 1, extract the model at least till 15GHz).

使用宽带模型。建议从DC提取至少到奈奎斯特频率的6倍（对于USB3.1Gen1，提取至少到
15GHz的模型）

• Check the board stack-up for accurate layer thickness and material properties.
– It is recommended to use Djordjevic-Sarkar models for the dielectric material definition.

检查板材堆叠是否准确，确保层厚和材料性能。

-建议使用Djordjevic-Sarkar模型来定义介电材料。

• Use accurate etch profiles and surface roughness for the signal traces across all layers in the stack-up.

使用精确的蚀刻轮廓和表面粗糙度的信号走线在所有层的堆叠。

• If the board layout is cut prior to extraction (to reduce simulation time), please define a cut boundary that is at least 0.25 inch away from the signal and power nets.

如果在提取之前切割电路板布局（以减少模拟时间），请定义距离信号和电源网络至少0.25 inch的切割边界。

• Check the via padstack definitions
– Ensure that the non-functional internal layer pads on signal vias are modeled the same way they would be fabricated.
– These non-functional internal layer pads on signal vias are not recommended by TI

检查via堆栈定义

-确保信号过孔上的非功能内层衬垫的建模方式与制造方式相同。

-TI不推荐在信号过孔上安装这些无功能的内层焊盘。

• Use Spice/S-parameter models (typically available from the vendor) for modeling all passives in the system

使用Spice/s参数模型（通常可从供应商处获得）对系统中的所有被动源进行建模。

4.2 Board-Model Validation 板子模型验证

The extracted board models need to be checked for the following properties:

提取的板模型需要检查以下属性：

• Passivity: This ensures that the board model is a passive network and does not generate energy.

无源性：确保单板模型是无源网络，不产生能量。

• Causality: This ensures that the board model obeys the causal relationship (output follows input).

因果关系：这确保板模型服从因果关系（输出遵循输入)。

These checks can be performed in any standard EDA simulator or extraction engine.

这些检查可以在任何标准的EDA模拟器或提取引擎中执行。