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SystemC在CPU/GPU验证中的应用（三）

       摘要：下面分享50个逐步升级SystemC编程能力的示例及建议的学习路线图。您可以一次一批地完成它们——从前五个基础的例子开始，然后转向channels, TLM, bus models, simple CPU/GPU kernels等等。在每个阶段掌握之后，再进行下一组的学习。

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50个代表性的SystemC例子

1. Hello, SystemC! (module + sc_main)
2. Simple clock generator
3. 4-bit up/down counter
4. Blocking FIFO channel
5. Non-blocking handshake channel
6. Combinational AND/OR modules
7. D-flip‐flop with async reset
8. 8×1 multiplexer
9. Simple RAM model (blocking accesses)
10. Simple ROM model
11. Dual-port RAM
12. Bus arbiter (round-robin)
13. TLM2.0 blocking transport (initiator)
14. TLM2.0 blocking transport (target)
15. TLM2.0 non-blocking transport
16. TLM2.0 analysis port / export
17. Simple AXI-Lite bus model
18. AXI-Lite master + slave example
19. Quantum keeper & time annotation
20. tlm_utils::simple_initiator_socket
21. tlm_utils::simple_target_socket
22. Hierarchical module instantiation
23. Dynamic process spawn & kill
24. Event notification & sc_event_queue
25. Reset synchronization circuit
26. Clock domain crossing FIFO
27. Bus monitor / tracer (TLM analysis)
28. Memory-mapped register file
29. Interrupt controller model
30. Pipeline stage model (fetch/decode/execute)
31. Simple 4-stage CPU datapath
32. Cache model (direct-mapped)
33. DMA engine model
34. GPGPU kernel launcher skeleton
35. GPU shader core (vector add)
36. Barrier synchronization (sc_barrier emulation)
37. Producer-consumer with sc_mutex
38. sc_semaphore example
39. SystemC-AMS basic RC filter
40. Fixed-point arithmetic with sc_fixed
41. Power‐aware sc_trace (VCD generation)
42. Cross-trade-off analysis (timing vs. power)
43. SystemC assertions (SC_ASSERT)
44. UVM-SystemC basic use case
45. Co-simulation stub (Verilog DPI)
46. SystemC Python binding stub
47. Parameterized module (SC_MODULE_T)
48. TLM-2.0 generic payload extensions
49. Simple NoC router model
50. Full mini‐SOC: CPU + L2 cache + memory + interconnect

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Third Batch: Examples 11–20

Below are the first five examples with complete code + detailed comments.

11. Dual-port RAM (阻塞访问)

文件名：dual_port_ram.cpp

#include <systemc.h>
#include <vector>// 定义 RAM 接口（阻塞）
struct ram_if : sc_interface {virtual unsigned int read(unsigned int addr, unsigned int port) = 0;virtual void write(unsigned int addr, unsigned int data, unsigned int port) = 0;
};// 双端口 RAM 模块
SC_MODULE(DualPortRAM) : public ram_if {std::vector<unsigned int> mem;sc_time latency;SC_CTOR(DualPortRAM): mem(256, 0)                // 256×32-bit, latency(sc_time(20, SC_NS)){}// 端口 port = 0 或 1unsigned int read(unsigned int addr, unsigned int port) override {wait(latency);if (addr < mem.size()) return mem[addr];return 0;}void write(unsigned int addr, unsigned int data, unsigned int port) override {wait(latency);if (addr < mem.size()) mem[addr] = data;}
};// Testbench
SC_MODULE(TB_DualPortRAM) {sc_port<ram_if> ram0, ram1;  // 两个端口SC_CTOR(TB_DualPortRAM) {SC_THREAD(proc0);SC_THREAD(proc1);}void proc0() {// 端口 0 先写for (unsigned i = 0; i < 8; ++i) {ram0->write(i, i*100, 0);cout << sc_time_stamp() << " P0 WRITE ["<< i <<"]="<< i*100 << endl;}wait(100, SC_NS);// 端口 0 读for (unsigned i = 0; i < 8; ++i) {unsigned d = ram0->read(i, 0);cout << sc_time_stamp() << " P0 READ  ["<< i <<"]="<< d << endl;}}void proc1() {// 稍后启动端口1，模拟并发wait(40, SC_NS);for (unsigned i = 0; i < 8; ++i) {ram1->write(i, i*1000, 1);cout << sc_time_stamp() << " P1 WRITE ["<< i <<"]="<< i*1000 << endl;}wait(100, SC_NS);for (unsigned i = 0; i < 8; ++i) {unsigned d = ram1->read(i, 1);cout << sc_time_stamp() << " P1 READ  ["<< i <<"]="<< d << endl;}sc_stop();}
};int sc_main(int, char*[]) {DualPortRAM ram("ram");TB_DualPortRAM tb("tb");tb.ram0(ram);tb.ram1(ram);sc_start();return 0;
}

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12. Bus Arbiter（轮询）

文件名：bus_arbiter.cpp

#include <systemc.h>// 简单 4-master 轮询仲裁器
SC_MODULE(Arbiter) {sc_in<bool> req[4];sc_out<bool> gnt[4];unsigned idx; // 下一个检查的 masterSC_CTOR(Arbiter): idx(0) {SC_METHOD(prioritize);for (int i = 0; i < 4; ++i)sensitive << req[i];}void prioritize() {// 清空所有 grantfor (int i = 0; i < 4; ++i) gnt[i].write(false);// 轮询检查请求for (int cnt = 0; cnt < 4; ++cnt) {unsigned i = (idx + cnt) % 4;if (req[i].read()) {gnt[i].write(true);idx = (i + 1) % 4; // 下次从 i+1 开始return;}}}
};// Testbench
SC_MODULE(TB_Arbiter) {sc_signal<bool> req[4], gnt[4];Arbiter arb;SC_CTOR(TB_Arbiter): arb("arb") {// 端口绑定for (int i = 0; i < 4; ++i) {arb.req[i](req[i]);arb.gnt[i](gnt[i]);}SC_THREAD(stimulus);SC_METHOD(monitor);for (int i = 0; i < 4; ++i) sensitive << gnt[i];}void stimulus() {// 不同 master 在不同时间发出请求req[0].write(true); wait(10, SC_NS);req[1].write(true); wait(10, SC_NS);req[0].write(false); wait(10, SC_NS);req[2].write(true); wait(10, SC_NS);req[1].write(false); req[2].write(false); req[3].write(true);wait(10, SC_NS);sc_stop();}void monitor() {cout << sc_time_stamp() << " grants:";