基于ads1256的ADC控制实现
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// -----------------------------------------------------------------------------
// Copyright (c) 2014-2025 All rights reserved
// -----------------------------------------------------------------------------
// Author : lvjitao lvjitao_o@163.com
// File : adc_ctrl_ads1256.v
// Create : 2025-10-18 09:06:14
// Revise : 2025-10-18 17:06:45
// Editor : sublime text3, tab size (4)
// -----------------------------------------------------------------------------
`timescale 1ns/1psmodule adc_ctrl_ads1256(//uartinput wire clk,input wire rst_n,input wire [7:0] pi_data_rx,input wire pi_flag_rx,output wire [7:0] po_data_tx,output wire po_flag_tx, //1256 spi interface\input wire miso,output wire cs_n,output reg sclk,output wire mosi,//1256 ads1256 signal\input wire drdy, //adctive lowoutput reg reset, //adctive lowoutput wire sync //adctive low);localparam IDLE = 10'b0000000001;
localparam PREPARE_C = 10'b0000000010;
localparam WREG = 10'b0000000100;
localparam SYNC_S = 10'b0000001000;
localparam WAKEUP = 10'b0000010000;
localparam WAIT1 = 10'b0000100000;
localparam RDATAC = 10'b0001000000;
localparam MISO = 10'b0010000000;
localparam WAIT2 = 10'b0100000000;
localparam SDATAC = 10'b1000000000;localparam RESET_MAX = 500 - 1;
localparam CLK_CNT_MAX = 50 - 1;
localparam STATE_CNT_MAX = 34;//cmd
localparam CMD_WREG = 24'h510078;
localparam CMD_SYNC = 8'hFC;
localparam CMD_WAKEUP = 8'h00;
localparam CMD_RDATAC = 8'h03;
localparam CMD_SDATAC = 8'h0F;reg [9:0] state;
reg [1:0] drdy_reg = 0;reg [8:0] reset_adc_cnt;reg [5:0] clk_cnt;
reg [5:0] state_cnt;
reg [56:0] shift_reg;reg mosi_wreg;assign cs_n = 1'b0;
assign sync = 1'b1;always @(posedge clk ) beginif (rst_n == 1'b0) begin// resetreset_adc_cnt <= 0;endelse if (reset_adc_cnt != RESET_MAX) beginreset_adc_cnt <= reset_adc_cnt + 1'b1;end
endalways @(posedge clk ) beginif (rst_n == 0) begin// resetreset <= 0;endelse if (reset_adc_cnt == RESET_MAX) beginreset <= 1;end
endalways @(posedge clk ) beginif (rst_n == 0) begin// resetstate <= 'd0;endelse case (state)IDLE: beginif (pi_flag_rx == 1'b1 && pi_data_rx == 8'hcc) beginstate <= PREPARE_C;endelse beginstate <= IDLE;endendPREPARE_C: beginif (drdy_reg == 2'b10) beginstate <= WREG;endelse beginstate <= PREPARE_C;endendWREG: beginif (state_cnt == STATE_CNT_MAX && clk_cnt == CLK_CNT_MAX) beginstate <= SYNC_S;endenddefault: state <= IDLE;endcase
endalways @(posedge clk ) begindrdy_reg <= {drdy_reg[0], drdy};
endalways @(posedge clk ) beginif (rst_n == 0) begin// resetclk_cnt <= 0;endelse if (state == WREG ) beginif (clk_cnt == CLK_CNT_MAX) beginclk_cnt <= 0;endelse beginclk_cnt <= clk_cnt + 1'b1;endend
endalways @(posedge clk ) beginif (rst_n == 0) begin// resetstate_cnt <= 0;endelse if (state == WREG ) beginif (state_cnt ==STATE_CNT_MAX && clk_cnt == CLK_CNT_MAX) beginstate_cnt <= 0;endelse if(clk_cnt == CLK_CNT_MAX) beginstate_cnt <= state_cnt + 1;endendelse beginstate_cnt <= 0;end
endalways @(posedge clk ) beginif (rst_n == 0) begin// resetsclk <= 0;endelse if (state == WREG && state_cnt <= 'd23) beginif (clk_cnt == CLK_CNT_MAX[6:1]) beginsclk <= 1'b1;endelse if (clk_cnt == CLK_CNT_MAX) beginsclk <= 1'b0;endendelse beginsclk <= 0;endendalways @(posedge clk ) beginif (rst_n == 0) begin// resetshift_reg <= {CMD_WREG, CMD_SYNC, CMD_WAKEUP, CMD_RDATAC, CMD_SDATAC};endelse if (state ==IDLE) beginshift_reg <= {CMD_WREG, CMD_SYNC,CMD_WAKEUP, CMD_RDATAC, CMD_SDATAC};endelse if (state == WREG && state_cnt >= 1'd1 &&state_cnt <= 'd24) beginif (clk_cnt == CLK_CNT_MAX[6:1]) beginshift_reg <= {shift_reg[54:0], 1'b0 };endend
endalways @(*) beginif (state == WREG && state_cnt <= 'd23) begin// reset mosi_wreg = shift_reg[55];endelse beginmosi_wreg = 1'b0;end
endendmodule
// -----------------------------------------------------------------------------
// Copyright (c) 2014-2025 All rights reserved
// -----------------------------------------------------------------------------
// Author : lvjitao lvjitao_o@163.com
// File : tb_adc_ctrl_ads1256.v
// Create : 2025-10-18 16:17:48
// Revise : 2025-10-18 16:32:02
// Editor : sublime text3, tab size (4)
// -----------------------------------------------------------------------------
`timescale 1ns/1psmodule tb_adc_ctrl_ads1256();reg clk, rst_n;
reg pi_flag;
reg [7:0] pi_data;wire sclk;
wire cs_n, mosi, miso, reset;
reg drdy;initial beginclk = 0;rst_n = 0;repeat(10) @(posedge clk);rst_n = 1;
endalways #10 clk = ~clk; initial begindrdy = 0;pi_flag = 0;pi_data = 0;#10;@(posedge rst_n);repeat(10) @(posedge clk);pi_flag <= 1;pi_data <= 8'hcc;@(posedge clk);pi_flag <= 1'b0;endinitial begin#10;gen_drdy();
endtask gen_drdy;integer i;beginfor(i=0; i<1000; i=i+1)begindrdy <= 0;#31000;drdy <= 1;#2333;endendendtaskadc_ctrl_ads1256 inst_adc_ctrl_ads1256(.clk (clk),.rst_n (rst_n),.pi_data_rx (pi_data_rx),.pi_flag_rx (pi_flag_rx),.po_data_tx (),.po_flag_tx (),.miso (miso),.cs_n (cs_n),.sclk (sclk),.mosi (mosi),.drdy (drdy),.reset (reset),.sync (sync));endmodule
