自定义半精度浮点数modelsim仿真显示

任务：仿真Verilog代码实现的半精度浮点数（fp16）乘法，需要把16位的半精度浮点数转为十进制数据显示，方便排查错误

在该Verilog文件添加能用于仿真的代码，不影响综合

moudle fp16mult();
//------------main code-------------
//always@(posedge clk) begin
//···
//end//···//-----------end main code---------------`ifdef SIMfunction real fp16_to_real;input [15:0] h;integer sign;integer exp;integer man;real frac;real val;beginsign = h[15];exp  = h[14:10];man  = h[9:0];if (exp == 0) beginif (man == 0) beginval = 0.0; // zeroend else begin// subnormal: value = (-1)^s * (man / 2^10) * 2^(1-bias)frac = man / 1024.0;val = frac * $pow(2.0, 1 - 15);endend else if (exp == 5'b11111) begin// Inf or NaNif (man == 0) beginval = 1.0/0.0; // +infend else beginval = 0.0/0.0; // NaNendend else begin// normalized: (-1)^s * (1 + man/2^10) * 2^(exp-bias)frac = 1.0 + (man / 1024.0);val = frac * $pow(2.0, exp - 15);endif (sign) fp16_to_real = -val; else fp16_to_real = val;endendfunction//注意：下面的变量是我想要看的半精度浮点数数据，weight、inputdata、outputdata、tmp2。根据自己代码设置变量real sim_weight_real;real sim_inputdata_real;real sim_outputdata_real;real sim_tmp2_real;real sim_tmp_real [KERNEL_SIZE*KERNEL_SIZE-1:0];integer sim_i;always @(*) beginsim_weight_real = fp16_to_real(weight);sim_inputdata_real = fp16_to_real(inputdata);sim_outputdata_real = fp16_to_real(outputdata);sim_tmp2_real = fp16_to_real(tmp2);end`endif
endmodule

仿真时在该文件开头添加`define SIM，综合时删除

`define SIM

注意不要在顶层文件中加，没用

该思路可用于其他自定义数据显示