FPGA即插即用Verilog驱动系列——按键消抖

实现功能：

单按键消抖，复用多个例化之后即可实现多按键

/***************************************************
*	Description		:  单按键消抖设计 
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module key_filter(Clk,       //50M时钟输入Rst_n,     //模块复位key_in,    //按键输入key_flag,  //按键标志信号key_state  //按键状态信号);input Clk;input Rst_n;input key_in;output reg key_flag;output reg key_state;localparamIDEL		= 4'b0001,FILTER0	= 4'b0010,DOWN		= 4'b0100,FILTER1 	= 4'b1000;reg [3:0]state;reg [19:0]cnt;reg en_cnt;	//使能计数寄存器//对外部输入的异步信号进行同步处理reg key_in_sa,key_in_sb;always@(posedge Clk or negedge Rst_n)if(!Rst_n)beginkey_in_sa <= 1'b0;key_in_sb <= 1'b0;endelse beginkey_in_sa <= key_in;key_in_sb <= key_in_sa;	endreg key_tmpa,key_tmpb;wire pedge,nedge;reg cnt_full;//计数满标志信号//使用D触发器存储两个相邻时钟上升沿时外部输入信号（已经同步到系统时钟域中）的电平状态always@(posedge Clk or negedge Rst_n)if(!Rst_n)beginkey_tmpa <= 1'b0;key_tmpb <= 1'b0;endelse beginkey_tmpa <= key_in_sb;key_tmpb <= key_tmpa;	end//产生跳变沿信号	assign nedge = !key_tmpa & key_tmpb;assign pedge = key_tmpa & (!key_tmpb);always@(posedge Clk or negedge Rst_n)if(!Rst_n)beginen_cnt <= 1'b0;state <= IDEL;key_flag <= 1'b0;key_state <= 1'b1;endelse begincase(state)IDEL :beginkey_flag <= 1'b0;if(nedge)beginstate <= FILTER0;en_cnt <= 1'b1;endelsestate <= IDEL;endFILTER0:if(cnt_full)beginkey_flag <= 1'b1;key_state <= 1'b0;en_cnt <= 1'b0;state <= DOWN;endelse if(pedge)beginstate <= IDEL;en_cnt <= 1'b0;endelsestate <= FILTER0;DOWN:beginkey_flag <= 1'b0;if(pedge)beginstate <= FILTER1;en_cnt <= 1'b1;endelsestate <= DOWN;endFILTER1:if(cnt_full)beginkey_flag <= 1'b1;key_state <= 1'b1;state <= IDEL;en_cnt <= 1'b0;endelse if(nedge)beginen_cnt <= 1'b0;state <= DOWN;endelsestate <= FILTER1;default:begin state <= IDEL; en_cnt <= 1'b0;		key_flag <= 1'b0;key_state <= 1'b1;endendcase	endalways@(posedge Clk or negedge Rst_n)if(!Rst_n)cnt <= 20'd0;else if(en_cnt)cnt <= cnt + 1'b1;elsecnt <= 20'd0;always@(posedge Clk or negedge Rst_n)if(!Rst_n)cnt_full <= 1'b0;else if(cnt == 20'd999_999)cnt_full <= 1'b1;elsecnt_full <= 1'b0;	endmodule