aurora接口ufc控流设计
UFC接口：slave接口的UFC用于发送UFC，master接口的UFC用于接受UFC
module aurora_rst_design
(
input i_clk,
input i_rst_n,
input i_ufc_start,
output reg o_ufc_tx_req,
output reg [63:0] o_ufc_tx_ms,
input i_ufc_tx_process,
input s_ufc_axis_ready,
output reg s_ufc_axis_valid,
output reg[63:0] s_ufc_axis_data
);
localparam IDLE = 3'd0;
localparam UFC_REQ_S = 3'd1;
localparam UFC_DATA_S = 3'd2;
reg[2:0]UFC_STATE;
reg[15:00] trans_cnt;
reg[15:00] trans_delay;
always@(posedge i_clk or negedge i_rst_n)begin
if(i_rst_n==1'b0)begin
UFC_STATE <= IDLE;
trans_cnt <= 'd0;
end
else begin
case(UFC_STATE)
IDLE:begin
if(i_ufc_start)begin
RST_STATE <= UFC_REQ_S;
o_ufc_tx_req <= 1'b1;
o_ufc_tx_ms <= 64'd127;//length
s_ufc_axis_valid <= 1'b1;
s_ufc_axis_data <= sof;
trans_cnt <= 'd0;
end
end
UFC_REQ_S:begin
if(s_ufc_axis_valid && s_ufc_axis_ready)begin
s_ufc_axis_data <= send_data;
trans_cnt <= trans_cnt + 'd1;
if(trans_cnt==o_ufc_tx_ms)begin
UFC_STATE <= UFC_DATA_S;
s_ufc_axis_valid <= 1'b0;
trans_cnt <= 'd0;
end
end
end
UFC_DATA_S:begin
trans_delay <= trans_delay + 1;//delay
if(trans_delay==15)begin
RST_STATE <= IDLE;
end
end
default:;
endcase
end
end
endmodule