VL25 输入序列连续的序列检测
`timescale 1ns/1ns
module sequence_detect(input clk,input rst_n,input a,output reg match);reg [4:0] state;
reg [4:0] next_state;parameter IDLE=5'd0,S1=5'd1,S2=5'd2,S3=5'd3,S4=5'd4,
S5=5'd5,S6=5'd6,S7=5'd7,S8=5'd8;always @(posedge clk or negedge rst_n) beginif (!rst_n) beginstate<=IDLE;// resetendelse beginstate<=next_state;end
endalways @(*) begincase(state)IDLE:beginif (a==1) beginnext_state<=IDLE;endelse beginnext_state<=S1;endendS1:beginif (a==1) beginnext_state<=S2;endelse beginnext_state<=S1;endendS2:beginif (a==1) beginnext_state<=S3;endelse beginnext_state<=S1;endendS3:beginif (a==1) beginnext_state<=S4;endelse beginnext_state<=S1;endendS4:beginif (a==0) beginnext_state<=S5;endelse beginnext_state<= IDLE;endendS5:beginif (a==0) beginnext_state<=S6;endelse beginnext_state<=S2;endend S6:beginif (a==0) beginnext_state<=S7;endelse beginnext_state<=S2;endendS7:beginif (a==1) beginnext_state<=S8;endelse beginnext_state<=S1;endendS8:beginif (a==0) beginnext_state<=S1;endelse beginnext_state<=IDLE;endend default:next_state<=IDLE; endcase
endalways @(posedge clk or negedge rst_n) beginif (!rst_n) beginmatch<=0;// resetendelse if (state==S8) beginmatch<=1;endelse beginmatch<=0;end
endendmodule
VL26 含无关项的序列检测
`timescale 1ns/1ns
module sequence_detect(input clk,input rst_n,input a,output reg match);reg [8:0] a_tem;
wire match_temp;always @(posedge clk or negedge rst_n) beginif (!rst_n) begina_tem <= 0;// resetendelse begina_tem <= {a_tem[7:0],a};end
endassign match_temp = ((a_tem[8:6]==3'b011)&&(a_tem[2:0]==3'b110)) ;always @(posedge clk or negedge rst_n) beginif (!rst_n) beginmatch <= 0;// resetendelse beginmatch<=match_temp;end
end
endmodule
VL27不重叠序列检测
`timescale 1ns/1ns
module sequence_detect(input clk,input rst_n,input data,output reg match,output reg not_match);parameter IDLE=0,s1=1,s2=2,s3=3,s4=4,s5=5,s6=6,FAIL=7;reg [2:0] cnt;
reg [2:0] state,next_state;always @(posedge clk or negedge rst_n) beginif (!rst_n) begincnt<=0;// resetendelse if (cnt=='d6) begincnt<=1;endelse begincnt<=cnt+1'b1;end
endalways @(posedge clk or negedge rst_n) beginif (!rst_n) beginstate<=IDLE;// resetendelse beginstate<=next_state;end
endalways @(*) begincase(state)IDLE:beginif (data==0&&cnt==0) beginnext_state=s1;endelse beginnext_state=FAIL;endends1:beginif (data==1) beginnext_state=s2;endelse beginnext_state=FAIL;endends2:beginif (data==1) beginnext_state=s3;endelse beginnext_state=FAIL;endends3:beginif (data==1) beginnext_state=s4;endelse beginnext_state=FAIL;endends4:beginif (data==0) beginnext_state=s5;endelse beginnext_state=FAIL;endends5:beginif (data==0) beginnext_state=s6;endelse beginnext_state=FAIL;endends6:beginif(data==0)beginnext_state=s1;endelsenext_state=FAIL;endFAIL:beginnext_state=(data==0&&cnt==6)?s1:FAIL;enddefault:next_state<=IDLE;endcase
endalways@(*)beginif (!rst_n) beginmatch=0;not_match=0;endelse beginmatch = cnt==6&&state==s6;not_match = cnt==6&&state==FAIL;end
endendmodule
VL28 输入序列不连续的序列检测
`timescale 1ns/1ns
module sequence_detect(input clk,input rst_n,input data,input data_valid,output reg match);parameter IDLE=0,s1=1,s2=2,s3=3,s4=4;
reg [2:0] state,next_state;always @(posedge clk or negedge rst_n) beginif (!rst_n) beginstate<=IDLE;// resetendelse beginstate<=next_state;end
endalways @(*) begincase(state)IDLE:next_state=(data==0&&data_valid==1)?s1:IDLE;s1:next_state=(data==1&&data_valid==1)?s2:IDLE;s2:next_state=(data==1&&data_valid==1)?s3:IDLE;s3:next_state=(data==0&&data_valid==1)?s4:IDLE;s4:next_state=(data==0&&data_valid==1)?s1:IDLE;endcase
endalways@(*)beginmatch=(state==s4);
endendmodule
VL29 信号发生器
`timescale 1ns/1ns
module signal_generator(input clk,input rst_n,input [1:0] wave_choise,output reg [4:0]wave);reg [4:0] cnt_sequare; //方波 周期20reg [4:0] cnt_sawtooth;//锯齿波 周期21reg [5:0] cnt_triangle;//三角波 周期20reg triangle_flag; //0代表下降 1 代表上升；always@(posedge clk or negedge rst_n)beginif(!rst_n)cnt_sequare<=5'b0;else if(wave_choise==2'd0)if(cnt_sequare<5'd19)cnt_sequare<=cnt_sequare+1'b1;elsecnt_sequare<=5'b0;elsecnt_sequare<=5'b0;endalways@(posedge clk or negedge rst_n)beginif(!rst_n)triangle_flag<=1'b0;else if(wave_choise==2'd2)if(wave==5'd1)triangle_flag<=1'b1;else if(wave==5'd19)triangle_flag<=1'b0;elsetriangle_flag<=triangle_flag;elsetriangle_flag<=1'b0;endalways@(posedge clk or negedge rst_n)beginif(!rst_n)wave<=5'd0;else case(wave_choise)2'd0 : wave <= (cnt_sequare == 9) ?20 : (cnt_sequare ==19) ? 0 :wave;2'd1 : wave <= (wave==20) ? 5'd0 : wave+1'b1;2'd2 : wave <= (triangle_flag==1'b0) ? wave-1'b1 : wave+1'b1;default :wave<=5'd0;endcaseend
endmodule
VL30 数据串转并电路
`timescale 1ns/1nsmodule s_to_p(input clk , input rst_n ,input valid_a ,input data_a ,output reg ready_a ,output reg valid_b ,output reg [5:0] data_b
);reg [2:0] cnt;
reg [5:0] temp;always @(posedge clk or negedge rst_n) beginif (!rst_n) begincnt<=0;// resetendelse if (valid_a&&ready_a)begincnt<=(cnt==5)?'d0:(cnt+1'b1);end
endalways @(posedge clk or negedge rst_n) beginif (!rst_n) begintemp<=0;// resetendelse if (valid_a&&ready_a) begintemp<={data_a,temp[5:1]};end
endalways @(posedge clk or negedge rst_n) beginif (!rst_n) begindata_b<=0;// resetendelse if (cnt=='d5) begindata_b<={data_a,temp[5:1]};endelse begindata_b<=data_b;end
endalways @(posedge clk or negedge rst_n) beginif (!rst_n) beginvalid_b<=0;// resetendelse if (cnt=='d5) beginvalid_b<=1;endelse beginvalid_b<=0;end
endalways @(posedge clk or negedge rst_n) beginif (!rst_n) beginready_a<=0;// resetendelse beginready_a<=1;end
endendmodule
VL31 数据累加输出
`timescale 1ns/1nsmodule valid_ready(input clk , input rst_n ,input [7:0] data_in ,input valid_a ,input ready_b ,output ready_a ,output reg valid_b ,output reg [9:0] data_out
);reg [1:0] cnt;always @(posedge clk or negedge rst_n) beginif (!rst_n) begincnt<=0;// resetendelse if (valid_a&&ready_a) begincnt<=cnt+1'b1;end
endalways @(posedge clk or negedge rst_n) beginif (!rst_n) begindata_out<=0;// resetendelse if (valid_a&&ready_a&&cnt!=0) begindata_out<=data_out+data_in;endelse if (valid_a&&ready_a&&cnt==0) begindata_out<=data_in;endelse begindata_out<=data_out;end
endalways @(posedge clk or negedge rst_n) beginif (!rst_n) beginvalid_b<=0;// resetendelse if (cnt==3&&valid_a&&ready_a) beginvalid_b<=1;endelse if(cnt==0&&valid_a&&ready_a) beginvalid_b<=0;endelse beginvalid_b<=valid_b;end
endassign ready_a = (!valid_b)|ready_b ;endmodule
VL32 非整数倍数据位宽转换24to128
`timescale 1ns/1nsmodule width_24to128(input clk , input rst_n ,input valid_in ,input [23:0] data_in ,output reg valid_out ,output reg [127:0] data_out
);reg [3:0] cnt;
reg [127:0] temp;always @(posedge clk or negedge rst_n) beginif (!rst_n) begincnt<=0;// resetendelse if (valid_in) begincnt<=cnt+1'b1;endelse begincnt<=cnt;end
endalways @(posedge clk or negedge rst_n) beginif (!rst_n) beginvalid_out<=0;// resetendelse if ((cnt==5||cnt==10||cnt==15)&&valid_in) beginvalid_out<=1;endelse beginvalid_out<=0;end
endalways @(posedge clk or negedge rst_n) beginif (!rst_n) begintemp<=0;// resetendelse begintemp<=valid_in?{temp[103:0],data_in}:temp;end
endalways@(posedge clk or negedge rst_n) beginif(~rst_n)data_out <= 0;else if(cnt==5)data_out <= valid_in? {temp[119:0], data_in[23:16]}: data_out;else if(cnt==10)data_out <= valid_in? {temp[111:0], data_in[23: 8]}: data_out;else if(cnt==15)data_out <= valid_in? {temp[103:0], data_in[23: 0]}: data_out;elsedata_out <= data_out;endendmodule
VL33 非整数倍数据位宽转换8to12
`timescale 1ns/1nsmodule width_8to12(input clk , input rst_n ,input valid_in ,input [7:0] data_in ,output reg valid_out,output reg [11:0] data_out
);reg [1:0] cnt;
reg [11:0] data_lock;always @(posedge clk or negedge rst_n) beginif (!rst_n) begincnt<=0;// resetendelse if (valid_in&&cnt<2) begincnt<=cnt+1;endelse if (valid_in&&cnt==2) begincnt<=0;endelsecnt<=cnt;
endalways @(posedge clk or negedge rst_n) beginif (!rst_n) beginvalid_out<=0;// resetendelse if (cnt==1&&valid_in) beginvalid_out<=1;endelse if (cnt==2&&valid_in) beginvalid_out<=1;endelsevalid_out<=0;
endalways @(posedge clk or negedge rst_n) beginif (!rst_n) begindata_lock<=0;// resetendelse if(valid_in) begindata_lock<=valid_in?{data_lock[3:0],data_in}:data_lock;end
endalways @(posedge clk or negedge rst_n) beginif (!rst_n) begindata_out<=0;// resetendelse if (cnt==1&&valid_in) begindata_out<={data_lock[7:0],data_in[7:4]};endelse if (cnt==2&&valid_in) begindata_out<={data_lock[3:0],data_in}; end
endendmodule
VL34 整数倍数据位宽转换8to16
`timescale 1ns/1nsmodule width_8to16(input clk , input rst_n ,input valid_in ,input [7:0] data_in ,output reg valid_out,output reg [15:0] data_out
);reg cnt;
reg [15:0] data_lock;always @(posedge clk or negedge rst_n) beginif (!rst_n) begincnt<=0;// resetendelse if (valid_in) begincnt<=cnt+1'b1;endelse begincnt<=cnt;end
endalways @(posedge clk or negedge rst_n) beginif (!rst_n) begindata_lock<=0; // resetendelse if (valid_in) begindata_lock<={data_lock[7:0],data_in};end
endalways @(posedge clk or negedge rst_n) beginif (!rst_n) begindata_out<=0;// resetendelse if (valid_in&&cnt==1) begindata_out<={data_lock[7:0],data_in};endelse begindata_out<=data_out;end
endalways @(posedge clk or negedge rst_n) beginif (!rst_n) beginvalid_out<=0;// resetendelse if (cnt==1&&valid_in) beginvalid_out<=1;endelse beginvalid_out<=0;end
endendmodule
VL35 状态机-非重叠的序列检测
`timescale 1ns/1nsmodule sequence_test1(input wire clk ,input wire rst ,input wire data ,output reg flag
);
//*************code***********//
parameter s0=0,s1=1,s2=2,s3=3,s4=4,s5=5;
reg [2:0] state,next_state;always @(posedge clk or negedge rst) beginif (!rst) beginstate<=s0;// resetendelse beginstate<=next_state;end
endalways@(*)begincase(state)s0:beginif (data) beginnext_state<=s1;endelse beginnext_state<=s0;endends1:beginif (!data) beginnext_state<=s2;endelse beginnext_state<=s1;endends2:beginif (data) beginnext_state<=s3;endelse beginnext_state<=s2;endends3:beginif (data) beginnext_state<=s4;endelse beginnext_state<=s3;endends4:beginif (data) beginnext_state<=s5;endelse beginnext_state<=s4;endends5:beginif (data) beginnext_state<=s1;endelse beginnext_state<=s0;endendendcase
endalways @(posedge clk or negedge rst) beginif (!rst) beginflag<=0;// resetendelse if (next_state==s5) beginflag<=1;endelse beginflag<=0;end
endendmodule
VL36 状态机-重叠序列检测
`timescale 1ns/1nsmodule sequence_test2(input wire clk ,input wire rst ,input wire data ,output reg flag
);
//*************code***********//
parameter s0=0,s1=1,s2=2,s3=3,s4=4;
reg [2:0] state,next_state;always @(posedge clk or negedge rst) beginif (!rst) beginstate<=s0;// resetendelse beginstate<=next_state;end
endalways@(*)begincase(state)s0:beginif (data) beginnext_state=s1;endelse beginnext_state=s0;endends1:next_state=(data)?s1:s2;s2:next_state=data?s3:s0;s3:next_state=data?s4:s2;s4:next_state=data?s1:s2;default:next_state=s0;endcase
endalways @(posedge clk or negedge rst) beginif (!rst) beginflag<=0;// resetendelse if (state==s4) beginflag<=1;endelse beginflag<=0;end
end//*************code***********//
endmodule
VL37 时钟分频（偶数）
`timescale 1ns/1nsmodule even_div(input wire rst ,input wire clk_in,output wire clk_out2,output wire clk_out4,output wire clk_out8);
//*************code***********//
reg cnt_2;
reg [1:0] cnt_4;
reg [2:0] cnt_8;reg clk_out2_t;
reg clk_out4_t;
reg clk_out8_t;always @(posedge clk_in or negedge rst) beginif (!rst) begincnt_2<=0;// resetendelse begincnt_2<=cnt_2+1'b1;end
endalways @(posedge clk_in or negedge rst) beginif (!rst) beginclk_out2_t<=0;// reset endelse if (cnt_2==1||cnt_2==0) beginclk_out2_t<=!clk_out2_t;end
endalways @(posedge clk_in or negedge rst) beginif (!rst) begincnt_4<=0;// resetendelse begincnt_4<=cnt_4+1'b1;end
endalways @(posedge clk_in or negedge rst) beginif (!rst) beginclk_out4_t<=0;// reset endelse if (cnt_4==0||cnt_4==2) beginclk_out4_t<=!clk_out4_t;end
endalways @(posedge clk_in or negedge rst) beginif (!rst) begincnt_8<=0;// resetendelse begincnt_8<=cnt_8+1'b1;end
endalways @(posedge clk_in or negedge rst) beginif (!rst) beginclk_out8_t<=0;// reset endelse if (cnt_8==4||cnt_8==0) beginclk_out8_t<=!clk_out8_t;end
endassign clk_out2 = clk_out2_t;
assign clk_out4 = clk_out4_t;
assign clk_out8 = clk_out8_t;
//*************code***********//
endmodule
VL38 自动贩售机1
`timescale 1ns/1ns
module seller1(input wire clk ,input wire rst ,input wire d1 ,input wire d2 ,input wire d3 ,output reg out1,output reg [1:0]out2
);
//*************code***********//
reg [3:0] cnt;
always @(posedge clk or negedge rst) beginif (!rst) begincnt<=0;// resetout1<=0;out2<=0;endelse beginif (d1) begincnt<=cnt+1;endelse if (d2) begincnt<=cnt+2;endelse if (d3) begincnt<=cnt+4;endelse if (cnt>=3) beginout1<=1;out2<=cnt-3;cnt<=0;endelse beginout1<=0;out2<=0;endend
end//*************code***********//
endmodule
VL39 自动贩售机2
`timescale 1ns/1ns
//状态机写法
module seller2(input wire clk ,input wire rst ,input wire d1 ,input wire d2 ,input wire sel ,output reg out1,output reg out2,output reg out3
);
//*************code***********//parameter S0=0, S0_5=1, S1=2, S1_5=3, S2=4, S2_5=5, S3=6;reg[2:0] state, nstate;always@(posedge clk or negedge rst) beginif(~rst)state <= 0;elsestate <= nstate;endalways@(*) begincase(state)S0 : nstate = d1? S0_5:d2? S1:nstate;S0_5 : nstate = d1? S1:d2? S1_5:nstate;S1 : nstate = d1? S1_5:d2? S2:nstate;S1_5 : nstate = ~sel? S0:d1? S2:d2? S2_5:nstate;S2 : nstate = ~sel? S0:d1? S2_5:d2? S3:nstate;default: nstate = S0;endcaseendalways@(*) beginif(~rst) begin{out1, out2, out3} = 3'b000;endelse begincase(state)S0, S0_5, S1: {out1, out2, out3} = 0;S1_5 : {out1, out2, out3} = ~sel? 3'b100: 3'b000;S2 : {out1, out2, out3} = ~sel? 3'b101: 3'b000;S2_5 : {out1, out2, out3} = ~sel? 3'b101: 3'b010;S3 : {out1, out2, out3} = ~sel? 3'b101: 3'b011;default : {out1, out2, out3} = 3'b000;endcaseendend
//*************code***********//
endmodule
VL40 占空比50%的奇数分频
`timescale 1ns/1nsmodule odo_div_or(input wire rst ,input wire clk_in,output wire clk_out7);//*************code***********//
reg clk_out7_d1;
reg clk_out7_d2;
reg [2:0] cnt;
always @(posedge clk_in or negedge rst) beginif (!rst) begincnt<=0;// resetendelse if(cnt==4) begincnt<=1;endelse begincnt<=cnt+1;end
endalways @(posedge clk_in or negedge rst) beginif (!rst) beginclk_out7_d1<=0;// resetendelse if (cnt==4) beginclk_out7_d1<=!clk_out7_d1;end
endalways @(negedge clk_in or negedge rst) beginif (!rst) beginclk_out7_d2<=0;// resetendelse if (cnt==4) beginclk_out7_d2<=!clk_out7_d2;end
endassign clk_out7 =clk_out7_d1&&clk_out7_d2 ;//*************code***********//
endmodule
VL42 无占空比要求的奇数分频
`timescale 1ns/1nsmodule odd_div ( input wire rst ,input wire clk_in,output wire clk_out5
);
//*************code***********//reg [2:0] cnt;
reg clk_out_temp;always @(posedge clk_in or negedge rst) beginif (!rst) begincnt<=0;// resetendelse if (cnt==4) begincnt<=0;endelse begincnt<=cnt+1'b1;end
endalways @(posedge clk_in or negedge rst) beginif (!rst) beginclk_out_temp<=0;// resetendelse if (cnt==0||cnt==2) beginclk_out_temp<=!clk_out_temp;end
endassign clk_out5 = clk_out_temp;//*************code***********//
endmodule
VL43 根据状态转移写状态机-三段式
`timescale 1ns/1nsmodule fsm1(input wire clk ,input wire rst ,input wire data ,output reg flag
);
//*************code***********//
parameter s0=0,s1=1,s2=2,s3=3;
reg [1:0] state,next_state;always @(posedge clk or negedge rst) beginif (!rst) beginstate<=s0;// resetendelse beginstate<=next_state;end
endalways@(*)begincase(state)s0:next_state=data?s1:s0;s1:next_state=data?s2:s1;s2:next_state=data?s3:s2;s3:next_state=data?s0:s3;default:next_state=s0;endcase
endalways @(posedge clk or negedge rst) beginif (!rst) beginflag<=0;// resetendelse if (state==s3&&data==1) beginflag<=1;endelse beginflag<=0;end
end//*************code***********//
endmodule
VL44 根据状态转移写状态机-二段式
`timescale 1ns/1nsmodule fsm2(input wire clk ,input wire rst ,input wire data ,output reg flag
);//*************code***********//
parameter s0=0,s1=1,s2=2,s3=3,s4=4;
reg [2:0] state,next_state;always @(posedge clk or negedge rst) beginif (!rst) beginstate<=s0;// resetendelse beginstate<=next_state;end
endalways@(*)begincase(state)s0:beginnext_state=data?s1:s0;flag=0;ends1:beginnext_state=data?s2:s1;flag=0;ends2:beginnext_state=data?s3:s2;flag=0; ends3:beginnext_state=data?s4:s3; flag=0;ends4:beginnext_state=data?s1:s0;flag=1;end endcase
end
//*************code***********//
endmodule
VL47格雷码计数器
`timescale 1ns/1nsmodule gray_counter(input clk,input rst_n,output reg [3:0] gray_out
);reg[4:0] count;reg rev;always@(posedge clk or negedge rst_n)if(!rst_n)count <= 5'b0;elsecount <= count + 1'b1;always@(*)if(!rst_n)gray_out = 4'b0;elsegray_out = count[4:1] ^ (count[4:1] >> 1);endmodule
VL48 多bitMUX同步器
`timescale 1ns/1nsmodule mux(input clk_a , input clk_b , input arstn ,input brstn ,input [3:0] data_in ,input data_en ,output reg [3:0] dataout
);reg [3:0] data_reg;
reg data_en_a,data_en_b0,data_en_b1;always @(posedge clk_a or negedge arstn) beginif (!arstn) begindata_reg<=0;// resetendelse begindata_reg<=data_in;end
endalways @(posedge clk_a or negedge arstn) beginif (!arstn) begindata_en_a<=0;// resetendelse begindata_en_a<=data_en;end
endalways @(posedge clk_b or negedge brstn) beginif (!brstn) begindata_en_b0<=0;// resetdata_en_b1<=0;endelse begindata_en_b0<=data_en_a;data_en_b1<=data_en_b0;end
endalways@(posedge clk_b or negedge brstn) beginif(~brstn)dataout <= 0;elsedataout <= data_en_b1? data_reg: dataout;
endendmodule
VL49 脉冲同步电路
`timescale 1ns/1nsmodule pulse_detect(input clk_fast , input clk_slow , input rst_n ,input data_in ,output dataout
);reg data_level, data_level1, data_level2, data_level3;// 脉冲信号转电平信号always@(posedge clk_fast or negedge rst_n) beginif(~rst_n)data_level <= 0;elsedata_level <= data_in? ~data_level: data_level;end// 电平信号打两拍再转为脉冲信号always@(posedge clk_slow or negedge rst_n) beginif(~rst_n) begindata_level1 <= 0;data_level2 <= 0;data_level3 <= 0;endelse begindata_level1 <= data_level;data_level2 <= data_level1;data_level3 <= data_level2;endendassign dataout = data_level3^data_level2;
endmodule
