[HDLBits] Cs450/timer
Implement a timer that counts down for a given number of clock cycles, then asserts a signal to indicate that the given duration has elapsed. A good way to implement this is with a down-counter that asserts an output signal when the count becomes 0.
实现一个 timer，该 timer 对给定的 clock cycles 数进行倒计时，然后断言一个信号以指示给定的持续时间已过。实现这一点的一个好方法是使用一个 down-counter，当 count 变为 0 时，它断言一个 output signal。
At each clock cycle:
在每个 clock cycle：
- If
load= 1, load the internal counter with the 10-bitdata, the number of clock cycles the timer should count before timing out. The counter can be loaded at any time, including when it is still counting and has not yet reached 0.
如果load= 1，则使用 10-bit数据加载内部计数器，这是 timer 在 timeout 之前应该计算的 clock cycles 数。计数器可以随时加载，包括当计数器仍在计数且尚未达到 0 时。 - If
load= 0, the internal counter should decrement by 1.
如果load= 0，则内部计数器应递减 1。
The output signal tc ("terminal count") indicates whether the internal counter has reached 0. Once the internal counter has reached 0, it should stay 0 (stop counting) until the counter is loaded again.
输出信号 tc （“terminal count”） 指示内部计数器是否已达到 0。一旦内部计数器达到 0，它应该保持 0 （停止计数），直到再次加载计数器。
Below is an example of what happens when asking the timer to count for 3 cycles:
以下是要求 timer 计数 3 个周期时发生的情况示例：
module top_module(input clk, input load, input [9:0] data, output tc
);reg [9:0] cnt;wire ena;assign ena = cnt == 0;assign tc = ena;//先做load的逻辑always@(posedge clk) beginif(load) begincnt <= data;endelse if (cnt > 0)begincnt <= cnt - 1; endelse begincnt <= cnt;endendendmodule