模拟集成电路设计与仿真 : PLL
前情提要
- 此為作者針對 PLL ，進行資料統整，以便日後查詢
原理
- CSDN : divider of PLL
- CSDN : affect of divider for phase noise, spur & jitter reduction
- 知乎 : affect of divider in type 1 & 2 PLL
1. Spur
- EETOP : phase noise V.S. spur
2. Phase Noise
- spectral regrowth
- reciprocal mixing
- 知乎 : Leeson's Model of PLL
- 知乎: equation & affect of phase noise (圖)
圖片來源 : 知乎: equation & affect of phase noise
圖片來源 : 知乎: equation & affect of phase noise
3. Jitter
- 知乎 : equation conversion from phase noise to RMS jitter
圖片來源 : MaZhaoxin's Blog : jitter
圖片來源 : EETOP : jitter
圖片來源 : EETOP : deterministic jitter V.S. random jitter
圖片來源 : EPSON : jitter
4. Capture Range V.S. Lock Range
- EETOP : hold range V.S. lock range V.S. pull-in range V.S. pull-out range
參考資料
- NTU : Design of Analog Integrated Circuits Chapter 12
- NTU : Design of Analog Integrated Circuits Chapter 13
- NTU : PLL