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SystemC在CPU/GPU验证中的应用（五）

       摘要：下面分享50个逐步升级SystemC编程能力的示例及建议的学习路线图。您可以一次一批地完成它们——从前五个基础的例子开始，然后转向channels, TLM, bus models, simple CPU/GPU kernels等等。在每个阶段掌握之后，再进行下一组的学习。

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50个代表性的SystemC例子

1. Hello, SystemC! (module + sc_main)
2. Simple clock generator
3. 4-bit up/down counter
4. Blocking FIFO channel
5. Non-blocking handshake channel
6. Combinational AND/OR modules
7. D-flip‐flop with async reset
8. 8×1 multiplexer
9. Simple RAM model (blocking accesses)
10. Simple ROM model
11. Dual-port RAM
12. Bus arbiter (round-robin)
13. TLM2.0 blocking transport (initiator)
14. TLM2.0 blocking transport (target)
15. TLM2.0 non-blocking transport
16. TLM2.0 analysis port / export
17. Simple AXI-Lite bus model
18. AXI-Lite master + slave example
19. Quantum keeper & time annotation
20. tlm_utils::simple_initiator_socket
21. tlm_utils::simple_target_socket
22. Hierarchical module instantiation
23. Dynamic process spawn & kill
24. Event notification & sc_event_queue
25. Reset synchronization circuit
26. Clock domain crossing FIFO
27. Bus monitor / tracer (TLM analysis)
28. Memory-mapped register file
29. Interrupt controller model
30. Pipeline stage model (fetch/decode/execute)
31. Simple 4-stage CPU datapath
32. Cache model (direct-mapped)
33. DMA engine model
34. GPGPU kernel launcher skeleton
35. GPU shader core (vector add)
36. Barrier synchronization (sc_barrier emulation)
37. Producer-consumer with sc_mutex
38. sc_semaphore example
39. SystemC-AMS basic RC filter
40. Fixed-point arithmetic with sc_fixed
41. Power‐aware sc_trace (VCD generation)
42. Cross-trade-off analysis (timing vs. power)
43. SystemC assertions (SC_ASSERT)
44. UVM-SystemC basic use case
45. Co-simulation stub (Verilog DPI)
46. SystemC Python binding stub
47. Parameterized module (SC_MODULE_T)
48. TLM-2.0 generic payload extensions
49. Simple NoC router model
50. Full mini‐SOC: CPU + L2 cache + memory + interconnect

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Fifth Batch: Examples 31–40

Below are the first five examples with complete code + detailed comments.

31. 简易 4 阶段 CPU 流水线: Fetch→Decode→Execute→Writeback

文件名：pipeline_4stage.cpp

#include <systemc.h>
#include <tuple>
#include <vector>// 指令格式：<opcode, operand>
using Instr   = std::pair<int,int>;
// 解码结果：<opcode, operand>
using Decoded = std::tuple<int,int>;
// 执行结果：<dest_reg, value>
using Result  = std::tuple<int,int>;// Fetch 阶段：从指令存储读 Instr
SC_MODULE(Fetch) {sc_in<bool>       clk;sc_fifo_out<Instr> out;std::vector<Instr> imem;int pc{0};SC_CTOR(Fetch) {// 初始化几条“指令”imem = {{0,5},{1,3},{0,2},{1,4},{2,0}};SC_METHOD(proc);sensitive << clk.pos();}void proc() {if (pc < (int)imem.size()) {Instr ins = imem[pc++];out.write(ins);cout<<sc_time_stamp()<<" [Fetch] pc="<<(pc-1)<<" instr=("<<ins.first<<","<<ins.second<<")\n";}}
};// Decode 阶段：把 Instr 转成 Decoded
SC_MODULE(Decode) {sc_in<bool>        clk;sc_fifo_in<Instr>   in;sc_fifo_out<Decoded> out;SC_CTOR(Decode) {SC_METHOD(proc);sensitive << clk.pos();}void proc() {Instr ins;if (in.nb_read(ins)) {Decoded d = std::make_tuple(ins.first, ins.second);out.write(d);cout<<sc_time_stamp()<<" [Decode] opcode="<<ins.first<<" operand="<<ins.second<<"\n";}}
};// Execute 阶段：  
// opcode 0→加1，1→乘2，2→写入寄存器 operand=寄存器号
SC_MODULE(Execute) {sc_in<bool>          clk;sc_fifo_in<Decoded>   in;sc_fifo_out<Result>   out;SC_CTOR(Execute) {SC_METHOD(proc);sensitive << clk.pos();}void proc() {Decoded d;if (in.nb_read(d)) {int op, val;std::tie(op,val) = d;int res = (op==0)? val+1 : (op==1)? val*2 : v