VESA时序检测模块设计verilog实现

module fps_vs_hs_de_timing_check
#(
parameter FPS             = 60,//帧率
parameter CLK_FREQ_CNT     = 74250000,//clock:单位HZ
parameter WIDTH            = 1920,//分辨率宽
parameter HIGH             = 1080//分辨率高
)
(
input            i_clk,
input            i_rst_n,

input            i_vs,
input            i_hs,

output reg            o_fps_err,
output reg            o_row_err,
output reg            o_col_err,

output reg    [31:0]    o_check_fps,
output reg    [31:0]    o_check_high,
output reg    [31:0]    o_check_width
);

reg    vs_r;
reg hs_r;

reg[31:0] col_cnt;
reg[31:0] row_cnt;


reg       start_flag;
reg[31:0] clk_cnt;
reg[31:0] frame_cnt;

always@(posedge i_clk or negedge i_rst_n)begin
if(i_rst_n==1'b0)begin
vs_r <= 1'b0;
hs_r <= 1'b0;
end
else begin
vs_r <= i_vs;
hs_r <= i_hs;
end
end

always@(posedge i_clk or negedge i_rst_n)begin
if(i_rst_n==1'b0)begin
col_cnt <= 'd0;
end
else begin
if(i_hs)begin
col_cnt <= col_cnt + 'd1;
end
else begin
col_cnt <= 'd0;
end
end
end

always@(posedge i_clk or negedge i_rst_n)begin
if(i_rst_n==1'b0)begin
o_check_width <= 'd0;
end
else begin
if(~i_hs & hs_r)begin
o_check_width <= col_cnt;
end
end
end


always@(posedge i_clk or negedge i_rst_n)begin
if(i_rst_n==1'b0)begin
row_cnt <= 'd0;
end
else if(~i_vs & vs_r)begin
row_cnt <= 'd0;
end
else if(i_vs) begin
if((~i_hs & hs_r)begin
row_cnt <= row_cnt + 'd1;
end
end
end

always@(posedge i_clk or negedge i_rst_n)begin
if(i_rst_n==1'b0)begin
o_check_high <= 'd0;
end
else begin
if(~i_vs & vs_r)begin
o_check_high <= row_cnt;
end
end
end

//clk_cnt
//start_flag
//frame_cnt

always@(posedge i_clk or negedge i_rst_n)begin
if(i_rst_n==1'b0)begin
start_flag <= 'd0;
end
else if(~vs_r & i_vs) begin
start_flag <= 1'b1;
end
end



always@(posedge i_clk or negedge i_rst_n)begin
if(i_rst_n==1'b0)begin
clk_cnt <= 'd0;
end
else  begin
if(clk_cnt==CLK_FREQ_CNT-1)begin
clk_cnt <= 'd0;
end
else begin
clk_cnt <= clk_cnt + 'd1;
end
end
end

always@(posedge i_clk or negedge i_rst_n)begin
if(i_rst_n==1'b0)begin
frame_cnt <= 'd0;
end
else if(clk_cnt ==(CLK_FREQ_CNT-1))begin
frame_cnt <= 'd0;
end
else if(clk_cnt < (CLK_FREQ_CNT-1)) begin
if(~vs_r & i_vs)begin
frame_cnt <= frame_cnt + 1;
end

end
end

always@(posedge i_clk or negedge i_rst_n)begin
if(i_rst_n==1'b0)begin
o_check_fps <= 'd0;
end
else if(clk_cnt ==(CLK_FREQ_CNT-1))  begin
o_check_fps <= frame_cnt;
end
end



always@(posedge i_clk or negedge i_rst_n)begin
if(i_rst_n==1'b0)begin
o_col_err <= 1'b0;
end
else if(o_check_width!=WIDTH) begin
o_col_err <= 1'b1;
end
else begin
o_col_err <= 1'b0;
end
end

always@(posedge i_clk or negedge i_rst_n)begin
if(i_rst_n==1'b0)begin
o_row_err <= 1'b0;
end
else if(o_check_high!=HIGH) begin
o_row_err <= 1'b1;
end
else begin
o_row_err <= 1'b0;
end
end

always@(posedge i_clk or negedge i_rst_n)begin
if(i_rst_n==1'b0)begin
o_fps_err <= 1'b0;
end
else if(o_check_fps>=(FPS-2)  o_check_fps<=(FPS+2)) begin//误差范围
o_fps_err <= 1'b0;
end
else begin
o_fps_err <= 1'b1;
end
end

endmodule