【PCIe 总线及设备入门学习专栏 5.1.3 -- PCIe PERST# 时序要求】

Overview

首先我们看下 PCIe x协议对 PERST 的要求：

A component must enter the LTSSM Detect state within 20 rms of the end of Fundamental Reset; With a Downstream Port that supports Link speeds greater than5.0 GT/s, software must wait a minimum of 100 ms after Link training completes before sending a Configuration Request to the device immediately below that Port.

什么是PERST#

PERST#作为 Fundamental Reset，是直接通过边带信号PERST#（PCI Express Reset）产生的。Fundamental Reset 会复位整个PCIe设备，初始化所有与状态机相关的硬件逻辑，端口状态以及配置空间中的配置寄存器等（every state machine and all the hardware logic, port states and configuration registers）。但是，也有