Nand2Tetris（计算机系统要素）学习笔记 Project 3

时序逻辑

0 DFF

跟Nand门一样，DFF门在我们的计算机体系中处于非常底层。可以说，计算机中的
所有时序芯片（寄存器、内存、计数器）都基于大量的DFF门。

• out（t） = in（t-1）

1 Bit

// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/3/a/Bit.hdl
/*** 1-bit register:* If load is asserted, the register's value is set to in;* Otherwise, the register maintains its current value:* if (load(t)) out(t+1) = in(t), else out(t+1) = out(t)*/
CHIP Bit {IN in, load;OUT out;PARTS:Mux(a = outT1, b = in, sel = load, out = inT);DFF(in = inT, out = out, out=outT1);
}

2 Register

// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/3/a/Register.hdl
/*** 16-bit register:* If load is asserted, the register's value is set to in;* Otherwise, the register maintains its current value:* if (load(t)) out(t+1) = int(t), else out(t+1) = out(t)*/
CHIP Register {IN in[16], load;OUT out[16];PARTS:Bit(in = in[0], load = load, out = out[0]);Bit(in = in[1], load = load, out = out[1]);Bit(in = in[2], load = load, out = out[2]);Bit(in = in[3], load = load, out = out[3]);Bit(in = in[4], load = load, out = out[4]);Bit(in = in[5], load = load, out = out[5]);Bit(in = in[6], load = load, out = out[6]);Bit(in = in[7], load = load, out = out[7]);Bit(in = in[8], load = load, out = out[8]);Bit(in = in[9], load = load, out = out[9]);Bit(in = in[10], load = load, out = out[10]);Bit(in = in[11], load = load, out = out[11]);Bit(in = in[12], load = load, out = out[12]);Bit(in = in[13], load = load, out = out[13]);Bit(in = in[14], load = load, out = out[14]);Bit(in = in[15], load = load, out = out[15]);}

3 RAM8

// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/3/a/RAM8.hdl
/*** Memory of eight 16-bit registers.* If load is asserted, the value of the register selected by* address is set to in; Otherwise, the value does not change.* The value of the selected register is emitted by out.*/
CHIP RAM8 {IN in[16], load, address[3];OUT out[16];PARTS:Not(in = address[0], out = n0);Not(in = address[1], out = n1);Not(in = address[2], out = n2);And(a = address[0], b = address[1], out = a1a0);And(a = address[0], b = address[2], out = a2a0);And(a = address[1], b = address[2], out = a2a1);And(a = n0, b = n1, out = n1n0);And(a = n0, b = n2, out = n2n0);And(a = n1, b = n2, out = n2n1);// 000 Register0And(a = n1n0, b = n2, out = n2n1n0);And(a = n2n1n0, b = load, out = load0);Register(in=in, load = load0, out = out0);// 001 Register1And(a = n2n1, b = address[0], out = n2n1a0);And(a = n2n1a0, b = load, out = load1);Register(in=in, load = load1, out = out1);// 010 Register2And(a = n2n0, b = address[1], out = n2a1n0);And(a = n2a1n0, b = load, out = load2);Register(in=in, load = load2, out = out2);// 011 Register3And(a = a1a0, b = n2, out = n2a1a0);And(a = n2a1a0, b = load, out = load3);Register(in=in, load = load3, out = out3);// 100 Register4And(a = n1n0, b = address[2], out = a2n1n0);And(a = a2n1n0, b = load, out = load4);Register(in=in, load = load4, out = out4);// 101 Register5And(a = a2a0, b = n1, out = a2n1a0);And(a = a2n1a0, b = load, out = load5);Register(in=in, load = load5, out = out5);// 110 Register6And(a = a2a1, b = n0, out = a2a1n0);And(a = a2a1n0, b = load, out = load6);Register(in=in, load = load6, out = out6);// 111 Register7And(a = a2a1, b = address[0], out = a2a1a0);And(a = a2a1a0, b = load, out = load7);Register(in=in, load = load7, out = out7);Mux8Way16(a = out0, b = out1, c = out2, d = out3, e = out4, f = out5, g = out6, h = out7, sel = address, out = out);}

4 RAM 64

// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/3/a/RAM64.hdl
/*** Memory of sixty four 16-bit RAM8_s.* If load is asserted, the value of the RAM8_ selected by* address is set to in; Otherwise, the value does not change.* The value of the selected RAM8_ is emitted by out.*/
CHIP RAM64 {IN in[16], load, address[6];OUT out[16];PARTS:Not(in = address[3], out = n0);Not(in = address[4], out = n1);Not(in = address[5], out = n2);And(a = address[3], b = address[4], out = a1a0);And(a = address[3], b = address[5], out = a2a0);And(a = address[4], b = address[5], out = a2a1);And(a = n0, b = n1, out = n1n0);And(a = n0, b = n2, out = n2n0);And(a = n1, b = n2, out = n2n1);// 000XXX RAM8// 543210// 000 RAM8_0And(a = n1n0, b = n2, out = n2n1n0);And(a = n2n1n0, b = load, out = load0);RAM8(in=in, load = load0, address=address[0..2], out = out0);// 001 RAM8_1And(a = n2n1, b = address[3], out = n2n1a0);And(a = n2n1a0, b = load, out = load1);RAM8(in=in, load = load1, address=address[0..2], out = out1);// 010 RAM8_2And(a = n2n0, b = address[4], out = n2a1n0);And(a = n2a1n0, b = load, out = load2);RAM8(in=in, load = load2, address=address[0..2], out = out2);// 011 RAM8_3And(a = a1a0, b = n2, out = n2a1a0);And(a = n2a1a0, b = load, out = load3);RAM8(in=in, load = load3, address=address[0..2], out = out3);// 100 RAM8_4And(a = n1n0, b = address[5], out = a2n1n0);And(a = a2n1n0, b = load, out = load4);RAM8(in=in, load = load4, address=address[0..2], out = out4);// 101 RAM8_5And(a = a2a0, b = n1, out = a2n1a0);And(a = a2n1a0, b = load, out = load5);RAM8(in=in, load = load5, address=address[0..2], out = out5);// 110 RAM8_6And(a = a2a1, b = n0, out = a2a1n0);And(a = a2a1n0, b = load, out = load6);RAM8(in=in, load = load6, address=address[0..2], out = out6);// 111 RAM8_7And(a = a2a1, b = address[3], out = a2a1a0);And(a = a2a1a0, b = load, out = load7);RAM8(in=in, load = load7, address=address[0..2], out = out7);Mux8Way16(a = out0, b = out1, c = out2, d = out3, e = out4, f = out5, g = out6, h = out7, sel = address[3..5], out = out);}

5 PC

reset	load	inc	sel[1]	sel[0]	内容
1	0	0	0	0	out(t+1) = 0
1	0	1	0	0	out(t+1) = 0
1	1	0	0	0	out(t+1) = 0
1	1	1	0	0	out(t+1) = 0
0	1	0	0	1	out(t+1) = in(t)
0	1	1	0	1	out(t+1) = in(t)
0	0	1	1	0	out(t+1) = out(t) + 1
0	0	0	1	1	out(t+1) = out(t)

// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/3/a/PC.hdl
/*** A 16-Register counter.* if      reset(t): out(t+1) = 0* else if load(t):  out(t+1) = in(t)* else if inc(t):   out(t+1) = out(t) + 1* else              out(t+1) = out(t)*/
CHIP PC {IN in[16],inc, load, reset;OUT out[16];PARTS:// reset; out0And16(a = in, b[0..15] = false, out = out0);// notResetAndLoad; out1 = inNot(in = reset, out = notReset);And(a = notReset, b = load, out = notResetAndLoad);// notResetNotLoadAndInc; out2Not(in = load, out = notLoad);And(a = notReset, b = notLoad, out = notResetNotLoad);And(a = notResetNotLoad, b = inc, out = notResetNotLoadAndInc);Inc16(in = out2T, out = out2);// notResetNotLoadNotInc; out3 = out3TNot(in = inc, out = notInc);And(a = notResetNotLoad, b = notInc, out = notResetNotLoadNotInc);Or(a = notResetAndLoad, b = notResetNotLoadNotInc, out = sel0);Mux4Way16(a = out0, b = in, c = out2, d = out3T, sel[0] = sel0, sel[1] = notResetNotLoad, out = outMux);Register(in = outMux, load = true, out = out, out = out3T, out = out2T);
}

6 RAM512

// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/3/b/RAM512.hdl
/*** Memory of 512 16-bit registers.* If load is asserted, the value of the register selected by* address is set to in; Otherwise, the value does not change.* The value of the selected register is emitted by out.*/
CHIP RAM512 {IN in[16], load, address[9];OUT out[16];PARTS:Not(in = address[6], out = n0);Not(in = address[7], out = n1);Not(in = address[8], out = n2);And(a = address[6], b = address[7], out = a1a0);And(a = address[6], b = address[8], out = a2a0);And(a = address[7], b = address[8], out = a2a1);And(a = n0, b = n1, out = n1n0);And(a = n0, b = n2, out = n2n0);And(a = n1, b = n2, out = n2n1);// 000XXXXXX RAM64// 876543210// 000 RAM64_0And(a = n1n0, b = n2, out = n2n1n0);And(a = n2n1n0, b = load, out = load0);RAM64(in=in, load = load0, address=address[0..5], out = out0);// 001 RAM64_1And(a = n2n1, b = address[6], out = n2n1a0);And(a = n2n1a0, b = load, out = load1);RAM64(in=in, load = load1, address=address[0..5], out = out1);// 010 RAM64_2And(a = n2n0, b = address[7], out = n2a1n0);And(a = n2a1n0, b = load, out = load2);RAM64(in=in, load = load2, address=address[0..5], out = out2);// 011 RAM64_3And(a = a1a0, b = n2, out = n2a1a0);And(a = n2a1a0, b = load, out = load3);RAM64(in=in, load = load3, address=address[0..5], out = out3);// 100 RAM64_4And(a = n1n0, b = address[8], out = a2n1n0);And(a = a2n1n0, b = load, out = load4);RAM64(in=in, load = load4, address=address[0..5], out = out4);// 101 RAM64_5And(a = a2a0, b = n1, out = a2n1a0);And(a = a2n1a0, b = load, out = load5);RAM64(in=in, load = load5, address=address[0..5], out = out5);// 110 RAM64_6And(a = a2a1, b = n0, out = a2a1n0);And(a = a2a1n0, b = load, out = load6);RAM64(in=in, load = load6, address=address[0..5], out = out6);// 111 RAM64_7And(a = a2a1, b = address[6], out = a2a1a0);And(a = a2a1a0, b = load, out = load7);RAM64(in=in, load = load7, address=address[0..5], out = out7);Mux8Way16(a = out0, b = out1, c = out2, d = out3, e = out4, f = out5, g = out6, h = out7, sel = address[6..8], out = out);}

7 RAM4K

// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/3/b/RAM4K.hdl
/*** Memory of 4K 16-bit registers.* If load is asserted, the value of the register selected by* address is set to in; Otherwise, the value does not change.* The value of the selected register is emitted by out.*/
CHIP RAM4K {IN in[16], load, address[12];OUT out[16];PARTS:Not(in = address[9], out = n0);Not(in = address[10], out = n1);Not(in = address[11], out = n2);And(a = address[9], b = address[10], out = a1a0);And(a = address[9], b = address[11], out = a2a0);And(a = address[10], b = address[11], out = a2a1);And(a = n0, b = n1, out = n1n0);And(a = n0, b = n2, out = n2n0);And(a = n1, b = n2, out = n2n1);// 000XXXXXX RAM512// 876543210// 000 RAM512_0And(a = n1n0, b = n2, out = n2n1n0);And(a = n2n1n0, b = load, out = load0);RAM512(in=in, load = load0, address=address[0..8], out = out0);// 001 RAM512_1And(a = n2n1, b = address[9], out = n2n1a0);And(a = n2n1a0, b = load, out = load1);RAM512(in=in, load = load1, address=address[0..8], out = out1);// 010 RAM512_2And(a = n2n0, b = address[10], out = n2a1n0);And(a = n2a1n0, b = load, out = load2);RAM512(in=in, load = load2, address=address[0..8], out = out2);// 011 RAM512_3And(a = a1a0, b = n2, out = n2a1a0);And(a = n2a1a0, b = load, out = load3);RAM512(in=in, load = load3, address=address[0..8], out = out3);// 100 RAM512_4And(a = n1n0, b = address[11], out = a2n1n0);And(a = a2n1n0, b = load, out = load4);RAM512(in=in, load = load4, address=address[0..8], out = out4);// 101 RAM512_5And(a = a2a0, b = n1, out = a2n1a0);And(a = a2n1a0, b = load, out = load5);RAM512(in=in, load = load5, address=address[0..8], out = out5);// 110 RAM512_6And(a = a2a1, b = n0, out = a2a1n0);And(a = a2a1n0, b = load, out = load6);RAM512(in=in, load = load6, address=address[0..8], out = out6);// 111 RAM512_7And(a = a2a1, b = address[9], out = a2a1a0);And(a = a2a1a0, b = load, out = load7);RAM512(in=in, load = load7, address=address[0..8], out = out7);Mux8Way16(a = out0, b = out1, c = out2, d = out3, e = out4, f = out5, g = out6, h = out7, sel = address[9..11], out = out);
}

8 RAM16K

// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/3/b/RAM16K.hdl
/*** Memory of 16K 16-bit registers.* If load is asserted, the value of the register selected by* address is set to in; Otherwise, the value does not change.* The value of the selected register is emitted by out.*/
CHIP RAM16K {IN in[16], load, address[14];OUT out[16];PARTS:Not(in = address[12], out = n0);Not(in = address[13], out = n1);// 00XXXXXXXXXXXX RAM4K// 13,12// 00 RAM4KAnd(a = n1, b = n0, out = n1n0);And(a = n1n0, b = load, out = load0);RAM4K(in=in, load = load0, address=address[0..11], out = out0);// 01 RAM4KAnd(a = n1, b = address[12], out = n1a0);And(a = n1a0, b = load, out = load1);RAM4K(in=in, load = load1, address=address[0..11], out = out1);// 10 RAM4KAnd(a = address[13], b = n0, out = a1n0);And(a = a1n0, b = load, out = load2);RAM4K(in=in, load = load2, address=address[0..11], out = out2);// 11 RAM4KAnd(a = address[12], b = address[13], out = a1a0);And(a = a1a0, b = load, out = load3);RAM4K(in=in, load = load3, address=address[0..11], out = out3);Mux4Way16(a = out0, b = out1, c = out2, d = out3, sel = address[12..13], out = out);
}