深度为16，位宽8bit的单端口SRAM——学习记录

 

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【Verilog HDL 训练】第 13 天（存储器、SRAM）-云社区-华为云

 

 module sram #(parameter ADDR_BITS=4)(input clk,input [ 7:0] addr,input [ 7:0] din,input ce,input we,output reg [ 7:0] dout);localparam MEM_DEPTH= 1<<ADDR_BITS;reg [7:0] mem[MEM_DEPTH-1:0];// synopsys_translate_offinteger i;initial beginfor(i=0; i<MEM_DEPTH;i=i+1) beginmem[i] = 8'h00;endend// synopsys_translate_onalways @(posedge clk) beginif(ce & we) beginmem[addr] <= din;endendalways @(posedge clk) beginif(ce && (!we)) begindout <= mem[addr];endendendmodule

`timescale 1ns / 1ps//// Company: // Create Date: 2019/05/16 21:04:57// Design Name: // Module Name: SRAM_tb//module sram_tb();reg [7 : 0] addr;reg [7 : 0]data_in;reg clk;reg we;reg ce;wire [7 : 0] data_out;integer i;//clock generationinitial beginclk = 0;forever#4 clk = ~clk;endinitial begince = 1'b0;we = 1'b0;addr = 4'd0;data_in = 8'h00;#20@(negedge clk)//readce = 1'b1;for (i = 0; i<16; i=i+1) begin@(negedge clk)addr = i;end@(negedge clk)//writewe = 1'b1;for (i = 0; i<16; i=i+1) begin@(negedge clk) beginaddr = i;data_in = data_in + 'h01;endend@(negedge clk)//readwe = 1'b0;for (i = 0; i<16; i=i+1) begin@(posedge clk)addr = i;end@(negedge clk)ce = 1'b0;//#100 $finish;#100 $stop;endsram #( .ADDR_BITS(4) ) u_sram(.clk(clk),.ce(ce),.we(we),.addr(addr),.din(data_in),.dout(data_out));endmodule