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摄像头数据分别传入两个bram中 Verilog代码

news 来源：原创 2025/5/11 17:44:36

1 代码

`timescale 1ns / 1ps

//摄像头数据分别传入两个bram中
module camera_to_2bram (
    input reset_n,
    input camera_clk,
    input camera_frame_valid_i,
    input [13:0] camera_data_i,
    output reg [16:0] write_addr,
    output reg [13:0] camera_data_to_bram,
    output buffer0_write_en,
    output buffer1_write_en
);


  localparam PIXEL_SIZE = 320 * 256;  //输入的每帧像素数量

  reg buffer0_write_flag, buffer1_write_flag;
  reg camera_frame_valid_i_d0;

  reg [13:0] camera_data_i_d0;


  //对帧有效信号打一拍
  always @(posedge camera_clk or negedge reset_n) begin
    if (!reset_n) begin
      camera_frame_valid_i_d0 <= 0;
    end else begin
      camera_frame_valid_i_d0 <= camera_frame_valid_i;
    end
  end

  //检测帧有效信号的上升沿
  assign frame_rise_edge = camera_frame_valid_i && !camera_frame_valid_i_d0;

  //每一帧开始换另一个bram写
  always @(posedge camera_clk or negedge reset_n) begin
    if (!reset_n) begin
      buffer0_write_flag <=