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【APB协议时序及示例】

news 2025/7/3 7:35:57

APB协议简介

1 APB简介
- 1.1 主要特点
- 1.2 APB信号列表
- 1.3 APB总线时序
- - 1.3.3 具体接口时序图
- 1.4 apb_sram的示例
- - 1.4.1 RTL
  - 1.4.2 TB

协议对我来说感觉真是常用常新，用过就忘；自己一开始是写过apb_slave的driver–及模拟apb_master的行为；后来实现apb和其他低俗外设协议的转换；
但基本上每次开始任务前还是都会遗忘掉；这次是要实现一个AXI2APB_bridge；在这里先简要回顾一下APB协议；

1 APB简介

APB：高级外设总线，主要是用来连接低速设备的；

1.1 主要特点

同步传输：信号在时钟上升沿上采样；
非流水线：每次传输至少2个时钟周期；
单主设备：通常是只有一个master；
低带宽：因为slave的ready时间长；

1.2 APB信号列表

图片如下图所示
在这里插入图片描述

1.3 APB总线时序

APB　Protocol手册上是明确分为两个阶段：setup 和 Access phase两个阶段；
具体对应状态机如下：
在这里插入图片描述

### 1.3.1 Setup Phase（第1个时钟周期）：
PSELx 置高，选择从设备。
PADDR 和 PWRITE 稳定。
PENABLE 保持低电平。

### 1.3.2 Access Phase（第2个时钟周期）：
PENABLE 置高，表示传输有效。
从设备在 PREADY=1 时完成读写操作。
如果 PREADY=0，主设备会等待（插入等待周期）。

1.3.3 具体接口时序图

具体接口时序图上可分为No wait和wait两种时序图；
也有的设计是assign pready = 1’b1;
在这里插入图片描述

1.4 apb_sram的示例

1.4.1 RTL

在这里重点关注在RTL中使用可综合的function用法；

`timescale 1ns / 1psmodule apb_sram #(parameter						   SIZE_IN_BYTES = 1024
)
(//----------------------------------// IO Declarations//----------------------------------input							   PRESETn,input							   PCLK,input							   PSEL,input [31:0]						PADDR,input							   PENABLE,input							   PWRITE,input [31:0]						PWDATA,output reg [31:0]				   PRDATA
);//----------------------------------// Local Parameter Declarations//----------------------------------localparam						  A_WIDTH = clogb2(SIZE_IN_BYTES);//----------------------------------// Variable Declarations//----------------------------------reg [31:0]						  mem[0:SIZE_IN_BYTES/4-1];wire								wren;wire								rden;wire [A_WIDTH-1:2]				  addr; //----------------------------------// Function Declarations//----------------------------------function integer clogb2;input [31:0]					value; reg [31:0]					  tmp; reg [31:0]					  rt;begintmp = value - 1;for (rt = 0; tmp > 0; rt = rt + 1) tmp = tmp >> 1;clogb2 = rt;endendfunction//----------------------------------// Start of Main Code//----------------------------------// Create read and write enable signals using APB control signalsassign wren = PWRITE && PENABLE && PSEL; // Enable Periodassign rden = ~PWRITE && ~PENABLE && PSEL; // Setup Periodassign addr = PADDR[A_WIDTH-1:2];// Write memalways @(posedge PCLK)beginif (wren)mem[addr] <= PWDATA;end// Read memalways @(posedge PCLK)beginif (rden)PRDATA <= mem[addr];elsePRDATA <= 'h0;endendmodule

1.4.2 TB

在这里重点关注看在测试中的task中的用法

`timescale 1ns / 1ps`ifndef CLK_FREQ
`define CLK_FREQ 50000000
`endifmodule top_tb();//----------------------------------// Local Parameter Declarations//----------------------------------parameter						   SIZE_IN_BYTES = 1024;localparam						  CLK_FREQ = `CLK_FREQ;localparam						  CLK_PERIOD_HALF = 1000000000/(CLK_FREQ*2);//----------------------------------// Variable Declarations//----------------------------------reg								 PRESETn = 1'b0;reg								 PCLK = 1'b0;reg								 PSEL;reg [31:0]						  PADDR;reg								 PENABLE;reg								 PWRITE;reg [31:0]						  PWDATA;   wire [31:0]						 PRDATA;reg [31:0]						  reposit[0:1023];//----------------------------------// Start of Main Code//----------------------------------apb_sram #(.SIZE_IN_BYTES				  (SIZE_IN_BYTES))u_apb_sram (.PRESETn						(PRESETn),.PCLK						   (PCLK),.PSEL						   (PSEL),.PADDR						  (PADDR),.PENABLE						(PENABLE),.PWRITE						 (PWRITE),.PWDATA						 (PWDATA),.PRDATA						 (PRDATA));// generate PCLKalways #CLK_PERIOD_HALF beginPCLK <= ~PCLK;end // generate PRESETninitial beginPRESETn <= 1'b0;repeat(5) @(posedge PCLK);PRESETn <= 1'b1;end// test memoryinitial beginPSEL = 1'b0;PADDR = ~32'h0;PENABLE = 1'b0;PWRITE = 1'b0;PWDATA = 32'hffff_ffff;wait(PRESETn == 1'b0);wait(PRESETn == 1'b1);repeat(3) @(posedge PCLK);memory_test(0, SIZE_IN_BYTES/4-1);repeat(5) @(posedge PCLK);$finish(2);end// memory test tasktask memory_test;// starting addressinput [31:0]					start;// ending address, inclusiveinput [31:0]					finish; reg [31:0]					  dataW;reg [31:0]					  dataR;integer						 a; integer						 b; integer						 err;beginerr = 0;// read-after-write testfor (a = start; a <= finish; a = a + 1) begindataW = $random;apb_write(4*a, dataW);apb_read (4*a, dataR);if (dataR !== dataW) beginerr = err + 1;$display($time,,"%m Read after Write error at A:0x%08x D:0x%x, but 0x%x expected", a, dataR, dataW);endendif (err == 0) $display($time,,"%m Read after Write 0x%x-%x test OK", start, finish);err = 0;// read_all-after-write_all testfor (a = start; a <= finish; a = a + 1) beginb = a - start;reposit[b] = $random;apb_write(4*a, reposit[b]);endfor (a = start; a <= finish; a = a + 1) beginb = a - start;apb_read(4*a, dataR);if (dataR !== reposit[b]) beginerr = err + 1;$display($time,,"%m Read all after Write all error at A:0x%08x D:0x%x, but 0x%x expected", a, dataR, reposit[b]);endendif (err == 0) $display($time,,"%m Read all after Write all 0x%x-%x test OK", start, finish);endendtask// APB write tasktask apb_write;input [31:0]					addr;input [31:0]					data;begin@(posedge PCLK);PADDR <= #1 addr;PWRITE <= #1 1'b1;PSEL <= #1 1'b1;PWDATA <= #1 data;@(posedge PCLK);PENABLE <= #1 1'b1;@(posedge PCLK);PSEL <= #1 1'b0;PENABLE <= #1 1'b0;endendtask// APB read tasktask apb_read;input [31:0]					 addr;output [31:0]					data;begin@(posedge PCLK);PADDR <= #1 addr;PWRITE <= #1 1'b0;PSEL <= #1 1'b1;@(posedge PCLK);PENABLE <= #1 1'b1;@(posedge PCLK);PSEL <= #1 1'b0;PENABLE <= #1 1'b0;data = PRDATA; // it should be blockingendendtask`ifdef VCSinitial begin$fsdbDumpfile("top_tb.fsdb");$fsdbDumpvars;endinitial begin`ifdef DUMP_VPD$vcdpluson();`endifend
`endifendmodule···

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